{"title":"A pipelined ASIC for color matrixing and convolution","authors":"K. Hsu, L. D'Luna, H. Yeh, W.A. Cook, G.W. Brown","doi":"10.1109/ASIC.1990.186140","DOIUrl":null,"url":null,"abstract":"A VLSI chip that can perform either 3*3 matrix multiplication or 3*3 digital convolution is discussed. Built-in self-test (BIST) techniques have been incorporated into the chip to ensure high fault coverage. The chip is designed in a 2- mu m CMOS technology using a silicon compiler for physical layout. The device is designed to operate at 14.3 MHz, making it suitable for real-time video and image processing applications.<<ETX>>","PeriodicalId":126693,"journal":{"name":"Third Annual IEEE Proceedings on ASIC Seminar and Exhibit","volume":"80 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1990-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Third Annual IEEE Proceedings on ASIC Seminar and Exhibit","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASIC.1990.186140","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 4
Abstract
A VLSI chip that can perform either 3*3 matrix multiplication or 3*3 digital convolution is discussed. Built-in self-test (BIST) techniques have been incorporated into the chip to ensure high fault coverage. The chip is designed in a 2- mu m CMOS technology using a silicon compiler for physical layout. The device is designed to operate at 14.3 MHz, making it suitable for real-time video and image processing applications.<>
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