System design considerations for a 5Gb/s source-synchronous link with common-mode clocking

Abstract

A 5Gb/s source-synchronous signaling system was developed utilizing embedded common-mode clocking technology to minimize clock distribution delays and to reduce the total pin count. The common-mode clocking scheme forwards the clock on the common mode of the differential data channels. In addition to the signal integrity issues present in differential signaling systems, the embedded common-mode clocking scheme presents additional challenges in system design. By means of impedance control for both common mode and differential mode, careful trace length matching, 5W spacing rule etc, we achieved good signal integrity and the link exhibits good margin. Mode conversion is one of the key issues in the common-mode clocking technology, and it is covered in detail. Measurement results show that the clocking scheme can tolerate −13dB mode conversion on both differential pairs at 5Gb/s.