A 10Gb/s Equalizer with Decision Feedback for High Speed Serial Links

Ali Kiaei, B. Matinpour, Ahmad Bahai, T. Lee
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引用次数: 7

Abstract

A 10 Gb/s equalizer using both feedforward and decision-feedback equalization is designed for high speed serial-links. The chip is implemented in a standard 0.25 mum SiGe BiCMOS technology with 50 GHz peak ft, and packaged in a commercial LLP package. Using a 4-stage feedforward and 2-tap post-cursor cancellation, this equalizer achieves a total peak-to-peak jitter of 27 ps and 33 ps for 10" and 20" of copper traces on FR4, respectively. The transmitter uses NRZ signaling with no pre-emphasis.
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高速串行链路的10Gb/s决策反馈均衡器
针对高速串行链路,设计了一种采用前馈和决策反馈均衡的10gb /s均衡器。该芯片采用标准的0.25 μ m SiGe BiCMOS技术,峰值频率为50 GHz,并封装在商用LLP封装中。使用4级前馈和2分导后光标消除,该均衡器在FR4上的10”和20”铜走线分别实现了27 ps和33 ps的峰对峰抖动。发射机使用无预强调的NRZ信号。
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