N. Papandreou, Nikolas Ioannou, Thomas P. Parnell, R. Pletka, M. Stanisavljevic, R. Stoica, Sasa Tomic, H. Pozidis
{"title":"Reliability of 3D NAND flash memory with a focus on read voltage calibration from a system aspect","authors":"N. Papandreou, Nikolas Ioannou, Thomas P. Parnell, R. Pletka, M. Stanisavljevic, R. Stoica, Sasa Tomic, H. Pozidis","doi":"10.1109/NVMTS47818.2019.8986221","DOIUrl":null,"url":null,"abstract":"This paper discusses the reliability challenges of 3D NAND flash memory and their impact on flash management for enterprise storage applications. Emphasis is given to the read voltage calibration and its critical role in achieving low error-rates and low latency read performance, as well as in enabling accurate block health estimation. We present experimental results that demonstrate the improvements in endurance, retention and read-disturb from different read voltage calibration schemes, and we address their requirements from a system perspective, i.e., the accuracy vs. complexity trade-off. We discuss the above aspects for state-of-the-art 3D TLC and QLC NAND flash memory.","PeriodicalId":199112,"journal":{"name":"2019 19th Non-Volatile Memory Technology Symposium (NVMTS)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"8","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2019 19th Non-Volatile Memory Technology Symposium (NVMTS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/NVMTS47818.2019.8986221","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 8
Abstract
This paper discusses the reliability challenges of 3D NAND flash memory and their impact on flash management for enterprise storage applications. Emphasis is given to the read voltage calibration and its critical role in achieving low error-rates and low latency read performance, as well as in enabling accurate block health estimation. We present experimental results that demonstrate the improvements in endurance, retention and read-disturb from different read voltage calibration schemes, and we address their requirements from a system perspective, i.e., the accuracy vs. complexity trade-off. We discuss the above aspects for state-of-the-art 3D TLC and QLC NAND flash memory.