Pub Date : 2019-10-01DOI: 10.1109/NVMTS47818.2019.8986219
Fei Mo, Yusaku Tagawa, T. Saraya, T. Hiramoto, M. Kobayashi
We have developed a numerical simulation framework for HfO2 based Ferroelectric Tunnel Junction (FTJ) memory using Non-Equilibrium Green Function (NEGF) and self-consistent potential method which is calibrated by our experimental FTJ results. Scalability and design guideline of Metal-Ferroelectric-Insulator-Semiconductor (MFIS) structure FTJ is investigated in this work. Due to the large asymmetry of dielectric screening length of MFIS structure FTJ electrodes, MFIS structure FTJ shows a higher tunneling electroresistance (TER) ratio than Metal-Ferroelectric-Insulator-Metal (MFIM) structure FTJ, while it has almost the same read current as MFIM structure FTJ. High read current and high TER ratio can be obtained by adjusting property of semiconductor bottom electrodes. A guideline of designing MFIS structure FTJ has been proposed for high read current and high TER ratio. MFIS type FTJ shows a potential for scaling down to sub-20 nm diameter.
{"title":"Scalability Study on Ferroelectric-HfO2 Tunnel Junction Memory Based on Non-equilibrium Green Function Method","authors":"Fei Mo, Yusaku Tagawa, T. Saraya, T. Hiramoto, M. Kobayashi","doi":"10.1109/NVMTS47818.2019.8986219","DOIUrl":"https://doi.org/10.1109/NVMTS47818.2019.8986219","url":null,"abstract":"We have developed a numerical simulation framework for HfO2 based Ferroelectric Tunnel Junction (FTJ) memory using Non-Equilibrium Green Function (NEGF) and self-consistent potential method which is calibrated by our experimental FTJ results. Scalability and design guideline of Metal-Ferroelectric-Insulator-Semiconductor (MFIS) structure FTJ is investigated in this work. Due to the large asymmetry of dielectric screening length of MFIS structure FTJ electrodes, MFIS structure FTJ shows a higher tunneling electroresistance (TER) ratio than Metal-Ferroelectric-Insulator-Metal (MFIM) structure FTJ, while it has almost the same read current as MFIM structure FTJ. High read current and high TER ratio can be obtained by adjusting property of semiconductor bottom electrodes. A guideline of designing MFIS structure FTJ has been proposed for high read current and high TER ratio. MFIS type FTJ shows a potential for scaling down to sub-20 nm diameter.","PeriodicalId":199112,"journal":{"name":"2019 19th Non-Volatile Memory Technology Symposium (NVMTS)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125045292","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-10-01DOI: 10.1109/NVMTS47818.2019.8986200
R. Tamura, N. Watanabe, H. Koike, Hideo Sato, Shoji Ikeda, T. Endoh, S. Sato
We have successfully developed, for the first time, a new memory test system for STT-MRAM at wafer-level where an electromagnet is combined with a memory test system and a 300 mm wafer prober. In the developed memory test system, an out-of-plane magnetic field up to ±800 mT can be applied on 10x10 mm2 in the 300 mm wafer with distribution of less than 2.5%. We demonstrated that the electromagnet can apply large enough magnetic field to evaluate magnetic immunity properties for STT-MRAM using 2Mb STT-MRAM; magnetic field dependence of pass-bit rate for “0”/“1” states, read/write shmoo, and “0”/“1” retention. All the properties can be explained by general theory for STT-MRAM. The developed memory test system with the electromagnet is a key testing tool for STT-MRAMs, which will contribute to increase efficiency of STT-MRAM testing as well as widening the application area of STT-MRAM sensitive to an external magnetic field.
{"title":"A novel memory test system with an electromagnet for STT-MRAM testing","authors":"R. Tamura, N. Watanabe, H. Koike, Hideo Sato, Shoji Ikeda, T. Endoh, S. Sato","doi":"10.1109/NVMTS47818.2019.8986200","DOIUrl":"https://doi.org/10.1109/NVMTS47818.2019.8986200","url":null,"abstract":"We have successfully developed, for the first time, a new memory test system for STT-MRAM at wafer-level where an electromagnet is combined with a memory test system and a 300 mm wafer prober. In the developed memory test system, an out-of-plane magnetic field up to ±800 mT can be applied on 10x10 mm2 in the 300 mm wafer with distribution of less than 2.5%. We demonstrated that the electromagnet can apply large enough magnetic field to evaluate magnetic immunity properties for STT-MRAM using 2Mb STT-MRAM; magnetic field dependence of pass-bit rate for “0”/“1” states, read/write shmoo, and “0”/“1” retention. All the properties can be explained by general theory for STT-MRAM. The developed memory test system with the electromagnet is a key testing tool for STT-MRAMs, which will contribute to increase efficiency of STT-MRAM testing as well as widening the application area of STT-MRAM sensitive to an external magnetic field.","PeriodicalId":199112,"journal":{"name":"2019 19th Non-Volatile Memory Technology Symposium (NVMTS)","volume":"139 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123561536","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-10-01DOI: 10.1109/NVMTS47818.2019.8986214
A. Levisse, M. Rios, W. Simon, P. Gaillardon, David Atienza Alonso
With the surge in complexity of edge workloads, it appeared in the scientific community that such workloads cannot be anymore overflown to the cloud due to the huge edge device to server communication energy cost and the high energy consumption induced in high end server infrastructure. In this context, edge devices must be able to efficiently process complex data-intensive workloads bringing in the concept of Edge AI. However, current architectures show poor energy efficiency while running data intensive workloads. While the community looks toward the integration of new memory architectures using emerging resistive memories and new specific accelerators, we propose a new concept to boost the energy efficiency of Edge systems running data intensive workloads: Functionality Enhanced Memories (FEM). FEM consist on a memory architecture with new functionalities at a decent area overhead cost. In this work, we demonstrate the feasibility of native transpose access for 1Transistor-1RRAM bitcells leveraging three independent gates transistors. Based on that, we thereby propose a concept of FEM-enabled Edge system embedding the proposed native transpose access RRAM-based memory architecture and an in-SRAM computing architecture (the BLADE).
{"title":"Functionality Enhanced Memories for Edge-AI Embedded Systems","authors":"A. Levisse, M. Rios, W. Simon, P. Gaillardon, David Atienza Alonso","doi":"10.1109/NVMTS47818.2019.8986214","DOIUrl":"https://doi.org/10.1109/NVMTS47818.2019.8986214","url":null,"abstract":"With the surge in complexity of edge workloads, it appeared in the scientific community that such workloads cannot be anymore overflown to the cloud due to the huge edge device to server communication energy cost and the high energy consumption induced in high end server infrastructure. In this context, edge devices must be able to efficiently process complex data-intensive workloads bringing in the concept of Edge AI. However, current architectures show poor energy efficiency while running data intensive workloads. While the community looks toward the integration of new memory architectures using emerging resistive memories and new specific accelerators, we propose a new concept to boost the energy efficiency of Edge systems running data intensive workloads: Functionality Enhanced Memories (FEM). FEM consist on a memory architecture with new functionalities at a decent area overhead cost. In this work, we demonstrate the feasibility of native transpose access for 1Transistor-1RRAM bitcells leveraging three independent gates transistors. Based on that, we thereby propose a concept of FEM-enabled Edge system embedding the proposed native transpose access RRAM-based memory architecture and an in-SRAM computing architecture (the BLADE).","PeriodicalId":199112,"journal":{"name":"2019 19th Non-Volatile Memory Technology Symposium (NVMTS)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127987201","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-10-01DOI: 10.1109/NVMTS47818.2019.9043368
P. Lomenzo, S. Slesazeck, M. Hoffmann, T. Mikolajick, U. Schroeder, B. Max
The influence of depolarization and its role in causing data retention failure in ferroelectric memories is investigated. Ferroelectric Hf0.5Zr0.5O2 thin films 8 nm thick incorporated into a metal-ferroelectric-metal capacitor are fabricated and characterized with varying thicknesses of an Al2O3 interfacial layer. The magnitude of the depolarization field is adjusted by controlling the thickness of the Al2O3 layer. The initial polarization and the change in polarization with electric field cycling is strongly impacted by the insertion of Al2O3 within the device stack. Transient polarization loss is shown to get worse with larger depolarization fields and data retention is evaluated up to 85 ° C.
{"title":"Ferroelectric Hf1-xZrxO2 memories: device reliability and depolarization fields","authors":"P. Lomenzo, S. Slesazeck, M. Hoffmann, T. Mikolajick, U. Schroeder, B. Max","doi":"10.1109/NVMTS47818.2019.9043368","DOIUrl":"https://doi.org/10.1109/NVMTS47818.2019.9043368","url":null,"abstract":"The influence of depolarization and its role in causing data retention failure in ferroelectric memories is investigated. Ferroelectric Hf<sub>0.5</sub>Zr<sub>0.5</sub>O<sub>2</sub> thin films 8 nm thick incorporated into a metal-ferroelectric-metal capacitor are fabricated and characterized with varying thicknesses of an Al<sub>2</sub>O<sub>3</sub> interfacial layer. The magnitude of the depolarization field is adjusted by controlling the thickness of the Al<sub>2</sub>O<sub>3</sub> layer. The initial polarization and the change in polarization with electric field cycling is strongly impacted by the insertion of Al<sub>2</sub>O<sub>3</sub> within the device stack. Transient polarization loss is shown to get worse with larger depolarization fields and data retention is evaluated up to 85 ° C.","PeriodicalId":199112,"journal":{"name":"2019 19th Non-Volatile Memory Technology Symposium (NVMTS)","volume":"386 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123359489","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-10-01DOI: 10.1109/NVMTS47818.2019.8986194
Alessandro Fumarola, Y. Leblebici, P. Narayanan, R. Shelby, L. L. Sanchez, G. Burr, Kibong Moon, J. Jang, H. Hwang, Severin Sidler
Crossbar arrays of non-volatile memory (NVM) devices represent one possible path for implementing highly energy-efficient neuromorphic computing systems. For Deep Neural Networks (DNN), where information can be encoded as analog voltage and current levels, such arrays can represent matrices of synaptic weights, implementing the matrix-vector multiplication needed for algorithms such as backpropagation in a massively-parallel fashion. Previous research demonstrated a large-scale hardware-software implementation based on phase-change memories and analyzed the potential speed and power advantages over GPU-based training. In this proceeding we will discuss extensions of this work leveraging a different class of memory elements. Using the concept of jump-tables we simulate the impact of real conductance response of non-filamentary resistive devices based on ${P} r_{0}.{}_{3}Ca_{0.7}$ Mn $O_{3}$ (PCMO). With the same approach as of [1], we simulate a three-layer neural network with training accuracy >90% on the MNIST dataset. The higher ON/OFF conductance ratio of improved Al[Mo/PCMO devices together with new programming strategies can lead to further accuracy improvement. Finally, we show that the bidirectional programming of Al[Mo/PCMO can be used to implement high-density neuromorphic systems with a single conductance per synapse, at only a slight degradation to accuracy.
{"title":"Non-filamentary non-volatile memory elements as synapses in neuromorphic systems","authors":"Alessandro Fumarola, Y. Leblebici, P. Narayanan, R. Shelby, L. L. Sanchez, G. Burr, Kibong Moon, J. Jang, H. Hwang, Severin Sidler","doi":"10.1109/NVMTS47818.2019.8986194","DOIUrl":"https://doi.org/10.1109/NVMTS47818.2019.8986194","url":null,"abstract":"Crossbar arrays of non-volatile memory (NVM) devices represent one possible path for implementing highly energy-efficient neuromorphic computing systems. For Deep Neural Networks (DNN), where information can be encoded as analog voltage and current levels, such arrays can represent matrices of synaptic weights, implementing the matrix-vector multiplication needed for algorithms such as backpropagation in a massively-parallel fashion. Previous research demonstrated a large-scale hardware-software implementation based on phase-change memories and analyzed the potential speed and power advantages over GPU-based training. In this proceeding we will discuss extensions of this work leveraging a different class of memory elements. Using the concept of jump-tables we simulate the impact of real conductance response of non-filamentary resistive devices based on ${P} r_{0}.{}_{3}Ca_{0.7}$ Mn $O_{3}$ (PCMO). With the same approach as of [1], we simulate a three-layer neural network with training accuracy >90% on the MNIST dataset. The higher ON/OFF conductance ratio of improved Al[Mo/PCMO devices together with new programming strategies can lead to further accuracy improvement. Finally, we show that the bidirectional programming of Al[Mo/PCMO can be used to implement high-density neuromorphic systems with a single conductance per synapse, at only a slight degradation to accuracy.","PeriodicalId":199112,"journal":{"name":"2019 19th Non-Volatile Memory Technology Symposium (NVMTS)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133677492","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-10-01DOI: 10.1109/NVMTS47818.2019.8986221
N. Papandreou, Nikolas Ioannou, Thomas P. Parnell, R. Pletka, M. Stanisavljevic, R. Stoica, Sasa Tomic, H. Pozidis
This paper discusses the reliability challenges of 3D NAND flash memory and their impact on flash management for enterprise storage applications. Emphasis is given to the read voltage calibration and its critical role in achieving low error-rates and low latency read performance, as well as in enabling accurate block health estimation. We present experimental results that demonstrate the improvements in endurance, retention and read-disturb from different read voltage calibration schemes, and we address their requirements from a system perspective, i.e., the accuracy vs. complexity trade-off. We discuss the above aspects for state-of-the-art 3D TLC and QLC NAND flash memory.
{"title":"Reliability of 3D NAND flash memory with a focus on read voltage calibration from a system aspect","authors":"N. Papandreou, Nikolas Ioannou, Thomas P. Parnell, R. Pletka, M. Stanisavljevic, R. Stoica, Sasa Tomic, H. Pozidis","doi":"10.1109/NVMTS47818.2019.8986221","DOIUrl":"https://doi.org/10.1109/NVMTS47818.2019.8986221","url":null,"abstract":"This paper discusses the reliability challenges of 3D NAND flash memory and their impact on flash management for enterprise storage applications. Emphasis is given to the read voltage calibration and its critical role in achieving low error-rates and low latency read performance, as well as in enabling accurate block health estimation. We present experimental results that demonstrate the improvements in endurance, retention and read-disturb from different read voltage calibration schemes, and we address their requirements from a system perspective, i.e., the accuracy vs. complexity trade-off. We discuss the above aspects for state-of-the-art 3D TLC and QLC NAND flash memory.","PeriodicalId":199112,"journal":{"name":"2019 19th Non-Volatile Memory Technology Symposium (NVMTS)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124116267","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-10-01DOI: 10.1109/NVMTS47818.2019.8986179
Panni Wang, Zheng Wang, Nujhat Tasneem, J. Hur, A. Khan, Shimeng Yu
In-memory computing with emerging non-volatile memories (NVMs) can accelerate the deep neural networks (DNNs) by parallelizing vector-matrix multiplication (VMM) operations in the analog domain. Hafnium Zirconium Oxide (HZO) based ferroelectric field-effect transistor (FeFET) shows great promise as a synaptic device for neuromorphic computing. The FeFET channel conductance could be tuned to map the weights in the neural network. DNNs’ weight update rules require that the weight of each synapse can be increased and decreased with multilevel states, which can be realized by applying positive or negative voltage pulses to change the polarization states of the HZO material. Therefore, HZO is expected to work on the minor loop instead of only working on the saturation loop of the ploarizion-voltage (P-V) hysteresis loop. To investigate the minor loop and partial switching dynamics, a TiN/HZO (10 nm, Hf:Zr=1:1)/TiN capacitor structure was fabricated by atomic layer deposition (ALD) with post-annealing. We established a testing protocol to measure the real-time polarization response corresponding to the voltage sequence applied. The results show that the polarity change increases by increasing the pulse amplitude and pulse width. Therefore, tuning the gate pulse amplitude and width could achieve multi-states of FeFET channel conductance.
{"title":"Investigating Dynamic Minor Loop of Ferroelectric Capacitor","authors":"Panni Wang, Zheng Wang, Nujhat Tasneem, J. Hur, A. Khan, Shimeng Yu","doi":"10.1109/NVMTS47818.2019.8986179","DOIUrl":"https://doi.org/10.1109/NVMTS47818.2019.8986179","url":null,"abstract":"In-memory computing with emerging non-volatile memories (NVMs) can accelerate the deep neural networks (DNNs) by parallelizing vector-matrix multiplication (VMM) operations in the analog domain. Hafnium Zirconium Oxide (HZO) based ferroelectric field-effect transistor (FeFET) shows great promise as a synaptic device for neuromorphic computing. The FeFET channel conductance could be tuned to map the weights in the neural network. DNNs’ weight update rules require that the weight of each synapse can be increased and decreased with multilevel states, which can be realized by applying positive or negative voltage pulses to change the polarization states of the HZO material. Therefore, HZO is expected to work on the minor loop instead of only working on the saturation loop of the ploarizion-voltage (P-V) hysteresis loop. To investigate the minor loop and partial switching dynamics, a TiN/HZO (10 nm, Hf:Zr=1:1)/TiN capacitor structure was fabricated by atomic layer deposition (ALD) with post-annealing. We established a testing protocol to measure the real-time polarization response corresponding to the voltage sequence applied. The results show that the polarity change increases by increasing the pulse amplitude and pulse width. Therefore, tuning the gate pulse amplitude and width could achieve multi-states of FeFET channel conductance.","PeriodicalId":199112,"journal":{"name":"2019 19th Non-Volatile Memory Technology Symposium (NVMTS)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128462125","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-10-01DOI: 10.1109/NVMTS47818.2019.8986178
D. Bimberg, T. Mikolajick, X. Wallart
The feasibility of the QD-Flash concept, its fast write and erase times, is demonstrated together with storage times of 4 days at room temperature. The storage time of holes in (InGa)Sb QDs embedded in a (AlGa)P matrix can be extended by growth modifications to 10 y. Tunneling structures were recently demonstrated to solve the trade-off conflict between storage time and erase time. A QD-NVSRAM is suggested to become the first commercial application.
{"title":"Novel Quantum Dot Based Memories with Many Days of Storage Time : Last Steps towards the Holy Grail?","authors":"D. Bimberg, T. Mikolajick, X. Wallart","doi":"10.1109/NVMTS47818.2019.8986178","DOIUrl":"https://doi.org/10.1109/NVMTS47818.2019.8986178","url":null,"abstract":"The feasibility of the QD-Flash concept, its fast write and erase times, is demonstrated together with storage times of 4 days at room temperature. The storage time of holes in (InGa)Sb QDs embedded in a (AlGa)P matrix can be extended by growth modifications to 10 y. Tunneling structures were recently demonstrated to solve the trade-off conflict between storage time and erase time. A QD-NVSRAM is suggested to become the first commercial application.","PeriodicalId":199112,"journal":{"name":"2019 19th Non-Volatile Memory Technology Symposium (NVMTS)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126932154","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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