RADJAM: A Novel Approach for Reduction of Soft Errors in Logic Circuits

K. Bhattacharya, N. Ranganathan
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引用次数: 13

Abstract

The task of achieving reliability against transient faults poses a significant challenge due to technology scaling trends. Several optimization techniques have been proposed in the literature for preventing soft errors in logic circuits. However, most approaches for avoiding soft errors in logic circuits have significant overheads in terms of delay, area or power. In this work, we propose a circuit level technique called RADJAM (RADiation JAMmer) to prevent soft errors, occurring due to radiation strikes, in logic cells. The RADJAM circuit when inserted at the output of a logic can reduce the generation of transient glitches significantly. Further, we propose an algorithm to insert RADJAM cells on selective nodes in a logic circuit. The algorithm uses signal logic probabilities and circuit slack for insertion of RADJAM cells on circuit nodes, thus improving the reliability of the logic circuit with minimal impact on the overall circuit delay. The proposed algorithm has been implemented and validated on the ISCAS85 benchmarks. Experimental results indicate that RADJAM optimized logic circuits can reduce soft error rates by around 39% with marginal delay, area and power overheads.
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RADJAM:一种减少逻辑电路软误差的新方法
由于技术的规模化趋势,实现瞬时故障可靠性的任务提出了重大挑战。为了防止逻辑电路中的软错误,文献中提出了几种优化技术。然而,大多数避免逻辑电路软错误的方法在延迟、面积或功率方面都有显著的开销。在这项工作中,我们提出了一种称为RADJAM(辐射干扰器)的电路级技术,以防止逻辑单元中由于辐射打击而发生的软错误。在逻辑输出端插入RADJAM电路可以显著减少瞬态故障的产生。此外,我们提出了一种将RADJAM单元插入逻辑电路中选择节点的算法。该算法利用信号逻辑概率和电路松弛在电路节点上插入RADJAM单元,从而在对整体电路延迟影响最小的情况下提高了逻辑电路的可靠性。该算法已在ISCAS85基准测试中得到了实现和验证。实验结果表明,RADJAM优化后的逻辑电路在最小延迟、最小面积和最小功耗的情况下,可将软错误率降低约39%。
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