{"title":"Efficient DC analysis of RVJ circuits for moment and derivative computations of interconnect networks","authors":"S. Batterywala, H. Narayanan","doi":"10.1109/ICVD.1999.745144","DOIUrl":null,"url":null,"abstract":"In this article we present a method for analysis of electrical networks containing positive resistors, voltage sources and current sources. We lay emphasis on computational aspects like size and positive definiteness of the resulting matrix. Currently the most popular method for analysis of such circuits is modified nodal analysis, which always yields a nonpositive definite matrix whenever voltage sources are present in the circuit. Our method constructs two minors of the underlying graph of the network and then uses these for writing KCE and KVE, thereby resulting in a symmetric positive definite system of equations of smaller size. We exploit the presence of voltage sources, and hence usually get a block diagonal structure in the matrix to be factored. Though our method is general enough and performs better than MNA for all DC circuits, it is specifically aimed towards solving DC circuits encountered during interconnect analysis.","PeriodicalId":443373,"journal":{"name":"Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013)","volume":"122 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1999-01-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"11","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICVD.1999.745144","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 11
Abstract
In this article we present a method for analysis of electrical networks containing positive resistors, voltage sources and current sources. We lay emphasis on computational aspects like size and positive definiteness of the resulting matrix. Currently the most popular method for analysis of such circuits is modified nodal analysis, which always yields a nonpositive definite matrix whenever voltage sources are present in the circuit. Our method constructs two minors of the underlying graph of the network and then uses these for writing KCE and KVE, thereby resulting in a symmetric positive definite system of equations of smaller size. We exploit the presence of voltage sources, and hence usually get a block diagonal structure in the matrix to be factored. Though our method is general enough and performs better than MNA for all DC circuits, it is specifically aimed towards solving DC circuits encountered during interconnect analysis.