Optimization of SC ΣΔ modulators based on worst-case-aware Pareto-optimal fronts

J. Zou, H. Graeb, D. Mueller, Ulf Schlichtmann
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引用次数: 5

Abstract

This paper presents an optimization method for switched-capacitor σ-δ modulators. The SNR performance is maximized while considering the performance capability of the critical building block, i.e. the Op Amp. Performance space exploration is applied to find the feasible region of the building block's performance, which is represented by a Pareto-optimal front. Through worst-case analysis on design points of the nominal Pareto front, a worst-case-aware Pareto-optimal front can be computed. The maximized SNR and the corresponding yield will be presented. The proposed optimization process is efficient and can be accomplished in some hours.
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基于最坏情况感知pareto最优前沿的SC ΣΔ调制器优化
本文提出了一种开关电容σ-δ调制器的优化方法。在考虑关键构建块即运放的性能能力的同时,实现信噪比性能的最大化。通过性能空间探索,找到构建块性能的可行区域,该可行区域用pareto最优前沿表示。通过对名义帕累托前线设计点的最坏情况分析,可以计算出一个感知最坏情况的帕累托最优前线。将给出最大信噪比和相应的产率。所提出的优化过程是高效的,可以在几个小时内完成。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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