A 1.2V single supply and low power, CMOS four-quadrant analog multiplier

Abstract

In this paper, a new low voltage topology for analog multiplier is presented. The circuit can be used with single low-power supply. The complete circuit has only twelve transistors; therefore, it satisfies the need for compact sub-circuit in analog VLSI systems. The mathematical discussion on the power consumption, total harmonic distortion and other features of the circuit and also simulation results in 0.18µm CMOS technology are presented. The results show 113µW power consumption with 1.2V single supply, 1.1% total harmonic distortion (THD) and 1GHz band-width.