Built-in test of CMOS state machines with realistic faults: a system perspective

Abstract

A built-in test system that is capable of parallel testing all combinational and sequential arrays on a CMOS chip is presented. The system is based on a recently introduced tristate multiplexing design for programmable and register logic arrays and requires minimal on-chip test storage and silicon area overhead. The test procedure is tailored to the detection of real mask defects in the layout of the array. The system also uses simple and economical data compaction circuit that provides a good fault coverage while not precluding the use of more sophisticated data compactors