On logic and transistor level design error detection of various validation approaches for PowerPC(TM) microprocessor arrays

Abstract

Design validation for embedded arrays remains as a challenging problem in today's microprocessor design environment. At Somerset, validation of array designs relies on both formal verification and vector simulation. Although several methods for army design validation have been proposed and had great success, little evidence has been reported for the effectiveness of these methods with respect to the detection of design errors. In this paper, the authors propose a way of measuring the effectiveness of different validation approaches based on automatic design error injection and simulation. The technique provides a systematic way for the evaluation of the quality of various validation approaches at both logic and transistor levels. Experimental results using different validation approaches on PowerPC microprocessor arrays will be reported.