On the implementation of an efficient performance driven generator for conditional-sum-adders

B. Becker, R. Drechsler, P. Molitor
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引用次数: 3

Abstract

The authors present data structures and an efficient algorithm realizing efficient performance driven generation of integer adders. The generator is parameterized in n, the operands' bitlength, and t/sub n/, the delay of the addition. It outputs an area minimal n-bit adder of the conditional-sum type with delay /spl les/t/sub n/, if such a circuit exists.<>
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条件加法器高效性能驱动生成器的实现
作者提出了数据结构和一种高效的算法,实现了高效的性能驱动的整数加法器生成。生成器的参数是n(操作数的位长)和t/sub n/(加法的延迟)。如果存在这样的电路,则输出具有延迟/spl /t/sub / n/的条件和类型的面积最小n位加法器。
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