Investigation of the possibility of using Single-Electron Transistors in Digital-to-Time Converters

Abstract

Single-Electron-Transistor (SET) features are exploited to improve the performance and the area of digital-to-time domain analog converters. There are two DTCs proposed in this research, DTC1 and DTC2, which have 4 and 8 transistors less compared with previous research, respectively. In the beginning, DTC1 and DTC2, are designed and simulated using CMOS transistors. Afterwards, the area, the power consumption and the delay parameters are discussed. In the rest, the mentioned DTCs are designed and simulated using SET instead of CMOS. Although power consumption and area were extremely reduced, it is shown that the delay parameter had an unacceptable increase. Finally, to overcome delay issue, combination of SET and CMOS was exploited to design and simulate DTCs. The simulations' results have shown improvement in delay parameter; especially it is found that Hybrid-DTC2 has the best performance in comparison with all designs.