Strained germanium-tin (GeSn) N-channel MOSFETs featuring low temperature N+/P junction formation and GeSnO2 interfacial layer

G. Han, S. Su, Lanxiang Wang, Wei Wang, X. Gong, Yue Yang, Ivana, P. Guo, Cheng Guo, Guangze Zhang, Jisheng Pan, Zheng Zhang, C. Xue, B. Cheng, Y. Yeo
{"title":"Strained germanium-tin (GeSn) N-channel MOSFETs featuring low temperature N+/P junction formation and GeSnO2 interfacial layer","authors":"G. Han, S. Su, Lanxiang Wang, Wei Wang, X. Gong, Yue Yang, Ivana, P. Guo, Cheng Guo, Guangze Zhang, Jisheng Pan, Zheng Zhang, C. Xue, B. Cheng, Y. Yeo","doi":"10.1109/VLSIT.2012.6242479","DOIUrl":null,"url":null,"abstract":"In this paper, we report the world's first germanium-tin (GeSn) channel nMOSFETs. Highlights of process module advances are: low temperature (400 °C) process for forming high quality n+/p junction with high dopant activation and reduced dopant diffusion; interface engineering achieved with GeSnO2 interfacial layer (IL) between high-k gate dielectric and GeSn channel. A gate-last process was employed. The GeSn nMOSFET with GeSnO2 IL demonstrates a substantially improved SS in comparison with Ge control, and an ION/IOFF ratio of 104.","PeriodicalId":266298,"journal":{"name":"2012 Symposium on VLSI Technology (VLSIT)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2012-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"28","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2012 Symposium on VLSI Technology (VLSIT)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIT.2012.6242479","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 28

Abstract

In this paper, we report the world's first germanium-tin (GeSn) channel nMOSFETs. Highlights of process module advances are: low temperature (400 °C) process for forming high quality n+/p junction with high dopant activation and reduced dopant diffusion; interface engineering achieved with GeSnO2 interfacial layer (IL) between high-k gate dielectric and GeSn channel. A gate-last process was employed. The GeSn nMOSFET with GeSnO2 IL demonstrates a substantially improved SS in comparison with Ge control, and an ION/IOFF ratio of 104.
查看原文
分享 分享
微信好友 朋友圈 QQ好友 复制链接
本刊更多论文
具有低温N+/P结形成和GeSnO2界面层的应变锗锡(GeSn) N沟道mosfet
在本文中,我们报道了世界上第一个锗锡(GeSn)沟道nmosfet。工艺模块进展的亮点是:低温(400°C)工艺,形成高质量的n+/p结,具有高掺杂激活和减少掺杂扩散;在高k栅极介质和GeSn通道之间采用GeSnO2界面层(IL)实现界面工程。采用了一种gate-last过程。与Ge对照相比,使用GeSnO2 IL的gsn nMOSFET的SS得到了显著改善,离子/IOFF比为104。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
求助全文
约1分钟内获得全文 去求助
来源期刊
自引率
0.00%
发文量
0
期刊最新文献
Varistor-type bidirectional switch (JMAX>107A/cm2, selectivity∼104) for 3D bipolar resistive memory arrays Segmented-channel Si1−xGex/Si pMOSFET for improved ION and reduced variability High performance bulk planar 20nm CMOS technology for low power mobile applications Conductive filament scaling of TaOx bipolar ReRAM for long retention with low current operation Strain-induced performance enhancement of tri-gate and omega-gate nanowire FETs scaled down to 10nm Width
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
0
微信
客服QQ
Book学术公众号 扫码关注我们
反馈
×
意见反馈
请填写您的意见或建议
请填写您的手机或邮箱
已复制链接
已复制链接
快去分享给好友吧!
我知道了
×
扫码分享
扫码分享
Book学术官方微信
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术
文献互助 智能选刊 最新文献 互助须知 联系我们:info@booksci.cn
Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。
Copyright © 2023 Book学术 All rights reserved.
ghs 京公网安备 11010802042870号 京ICP备2023020795号-1