{"title":"At the core of system scaling","authors":"G. Yeric","doi":"10.1109/ESSDERC.2016.7599574","DOIUrl":null,"url":null,"abstract":"This paper will examine challenges in future device scaling and the implications arising from difficulties in delivering scaling benefits from devices to the circuit level, and ultimately up to the system level. These implications will serve to highlight opportunities in design-technology interactions to aid in overall system scaling.","PeriodicalId":246471,"journal":{"name":"ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference","volume":"83 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ESSDERC.2016.7599574","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
This paper will examine challenges in future device scaling and the implications arising from difficulties in delivering scaling benefits from devices to the circuit level, and ultimately up to the system level. These implications will serve to highlight opportunities in design-technology interactions to aid in overall system scaling.
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