BIST with negligible aliasing through random cover circuits

Abstract

In this paper, a new modified BIST structure is investigated. The output of the MISA is monitored during the test by an error detection circuit which is composed of two simple cover circuits. To simplify the cover construction, the cover circuits are randomly chosen to be active for some of the outputs of the MISA. Thus, a time-consuming fault simulation can be completely avoided. The overhead for the cover circuits is determined for several of the ISCAS'85 and Berkeley benchmark circuits. These simulation experiments show that a significant reduction of the aliasing probability can be achieved, confirming and far surpassing theoretically predicted improvements. Moreover, this improvement can be achieved at a nearly negligible cost in additional hardware.