Ultra-shallow junctions for novel device architectures beyond 65 nm node

Abstract

The most recent release of the ITRS, the 2003 edition, describes a paradigm change in Si chip manufacturing expected around the 65 nm node. This is due to the rapid introduction of new materials and device structures required for further scaling of performance, such as strained Si, ultra-thin-body and multiple metal-gate devices. These novel architectures raise fundamentally new questions for shallow junction formation. We discuss several related issues from the perspective of future challenges for ion implantation and rapid thermal annealing: whether high tilt implantation is necessary to achieve sufficient extension overlap; is an ultra-shallow junction technology required for thin body devices; the role of ion implantation in metal-gate technology; and the challenge for RTP in an era of ever increasing system on chip integration and shrinking thermal budgets.