Study of reliable via structure for Fan Out Panel Level Package (FoPLP)

Da-Hee Kim, Jae-Ean Lee, Gyujin Choi, Sunguk Lee, Giho Jeong, Hongwon Kim, S. Lee, Dong Wook Kim
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引用次数: 2

Abstract

The fan out technology has been recently introduced as an effective method to reduce a packaging cost and to minimize a package size by using a redistribution layer(RDL). Moreover, as the number of high-capacity ultra-small devices increases, transition to fan-out package technology (FOPKG) is an important for realizing fast signal speed and high capacity. To this end, one of the key parameters for FOPKG’s interconnection density and fine pitch is adopting the stacked fine via technology.In this paper, we propose the physical crack mode of the stacked via in the fan-out panel level package(FOPLP), and try to optimize structural integrity based on the crack generation mechanism. Physical crack in stacked vias occurs in two different modes: via-via interface crack, via-dielectric point crack. To investigate via-via interface crack, various via shapes were tested. As a result, vias with lower dimple showed better structural stability under temperature changing condition. For via-dielectric point crack, structural DOE for tapered via angle was performed, and an optimal angle with released stress between cu and dielectric could be found. Furthermore, it was found that physical crack occurs depending on via size. Thus, in order to secure reliability margin, a study was conducted to change in shape and reinforce the weak point.In summary, as a result of the above study, it could be possible to optimize the via structure. The package reliability tests (Pre-condition + TC / u-HAST, HTS) were successfully evaluated with a vehicle that is adopted by optimal triple stacked via structure. By using the stacked via optimized through this study, the characteristics of FOPKG can be further improved by high electrical performance and the reduction of package size.
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扇出面板级封装(FoPLP)可靠通孔结构研究
扇出技术最近被引入,作为一种有效的方法,以减少包装成本,并通过使用再分配层(RDL)最小化包装尺寸。此外,随着高容量超小型器件数量的增加,向扇出封装技术(FOPKG)过渡是实现快速信号速度和高容量的重要手段。为此,FOPKG互连密度和细间距的关键参数之一是采用堆叠细通孔技术。本文提出了扇出板级封装(FOPLP)中堆叠通孔的物理裂纹模式,并尝试基于裂纹产生机制对结构完整性进行优化。叠合过孔的物理裂纹以两种不同的模式出现:过孔-过孔界面裂纹和过孔-介电点裂纹。为了研究孔-孔界面裂纹,对不同形状的孔进行了测试。结果表明,在温度变化条件下,凹窝越小的通孔结构稳定性越好。对于过介电点裂纹,进行了锥形过孔角的结构DOE计算,得到了cu -介电点释放应力的最佳角度。此外,发现物理裂纹的发生与孔的尺寸有关。因此,为了确保可靠性裕度,进行了改变形状和加强弱点的研究。综上所述,通过上述研究,可以对通孔结构进行优化。采用最优三叠通孔结构的整车,成功地进行了封装可靠性测试(Pre-condition + TC / u-HAST, HTS)。通过本研究优化的堆叠通孔,可以进一步提高FOPKG的电性能,减小封装尺寸。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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