Low power computing using STT-MRAM

Abstract

The computing systems are scaling down 100 times every decade, while the processing power doubles every two years. As a result, the power density has been the one of the most critical issues that limit the modern processors. Therefore, new technologies and computer architectures are under tensed development to reduce the power consumption. Magnetic tunnel junction (MTJ) nanopillar with the advantages of non-volatility, fast switching speed, and high density promises new designs and architectures to significantly alleviate the power issue. Meanwhile, it could be stacked on top of CMOS circuits to break the bottleneck of memory bandwidth limitation. This paper presents new designs of the non-volatile logic gates, which are compared with the conventional designs including non-volatile flip-flops, fully non-volatile logic gates, and hybrid non-volatile logic gates. The simulation results show that proposed non-volatile logic gates have the advantage of low power, especially at the low switching frequency. The proposed XOR has reduced the power consumption of XOR in the conventional load/save systems by 45% at high switching frequency, and 92% at 100 kHz. The proposed designs also show the advantage of reconfigurability, which makes the designs more flexible and robust.