A 0.004-mm2 O.7-V 31.654-μW BPSK Demodulator Incorporating Dual-Path Loop Self-Biased PLL

Abstract

This paper presents a low-supply binary-phase-shift-keying (BPSK) demodulator based on an area- and power-efficiency phase-locked loop (PLL) for wireless power biomedical implants with high-quality factor (Q) coils. The dual-path loop self-biased PLL is proposed to reduce the area of the integral capacitor and is insensitive to the process, voltage, and temperature (PVT) variations. Hence, our PLL can be designed with a wide loop bandwidth to increase the maximum input data rate of the demodulator. Designed in a 40-nm CMOS process with a tiny core area of 0.004 mm2, our BPSK demodulator merely consumes 31.654 μW with a 0.7-V supply voltage. Simulations show that our BPSK demodulator can deliver at the maximum data rate of 847.5 kb/s operating at a 13.56-MHz carrier frequency under different process corners.