Pub Date : 2022-11-11DOI: 10.1109/APCCAS55924.2022.10090267
Xiang Li, Dongsheng Liu, Ang Hu, Aobo Li, Shuo Yang, Jiahao Lu, Jianming Lei
Pseudo-random number extension and hashing limit the time for encryption and decryption in multiple lattice-based post-quantum cryptography (PQC). Keccak is a crucial part in pseudo-random number extension and hashing, being the most restrictive module. With the requirement of high-performance, it is important to implement a configurable Keccak core with flexibility and high throughput. In this paper, a novel structure of high throughput pseudo-random number extension generator is proposed. The method utilizes two-stage series round function circuits to reduce cycles in half. And benefiting from combining the p, π, σ, and I steps into a single step in the Keccak, the logic resource overhead is reduced. It can be configured to support multiple sampling strategies including central binomial distribution and rejection. This work is implemented on ZYNQ UltraScale+ FPGA platform with the highest throughput of 11.7Gbps. Compared to related works, the high-throughput and configurability make the proposed pseudo-random number extension generator suitable for various lattice-based cryptographic schemes.
{"title":"A High Throughput and Configurable Pseudo-random Number Extension Generator for Lattice-based Post-quantum Cryptography","authors":"Xiang Li, Dongsheng Liu, Ang Hu, Aobo Li, Shuo Yang, Jiahao Lu, Jianming Lei","doi":"10.1109/APCCAS55924.2022.10090267","DOIUrl":"https://doi.org/10.1109/APCCAS55924.2022.10090267","url":null,"abstract":"Pseudo-random number extension and hashing limit the time for encryption and decryption in multiple lattice-based post-quantum cryptography (PQC). Keccak is a crucial part in pseudo-random number extension and hashing, being the most restrictive module. With the requirement of high-performance, it is important to implement a configurable Keccak core with flexibility and high throughput. In this paper, a novel structure of high throughput pseudo-random number extension generator is proposed. The method utilizes two-stage series round function circuits to reduce cycles in half. And benefiting from combining the p, π, σ, and I steps into a single step in the Keccak, the logic resource overhead is reduced. It can be configured to support multiple sampling strategies including central binomial distribution and rejection. This work is implemented on ZYNQ UltraScale+ FPGA platform with the highest throughput of 11.7Gbps. Compared to related works, the high-throughput and configurability make the proposed pseudo-random number extension generator suitable for various lattice-based cryptographic schemes.","PeriodicalId":243739,"journal":{"name":"2022 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125100205","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-11-11DOI: 10.1109/APCCAS55924.2022.10090258
Shaohang Chu, Yan Li, Xu Cheng, Xiaoyang Zeng
Soft error is one of the main circuit reliability issues. Mitigating soft error inevitably requires sacrificing area and power, therefore, it is necessary to balance area, power, and soft error. In this paper, some improvements have been made to the multi-objective optimization framework based on Back Propagation (BP) neural network and Non-dominated Sorting Genetic Algorithm-II (NSGA-II). A data set selection and dimensionality reduction scheme is proposed to ensure that the framework is suitable for circuit designs of different scales. The experimental results show that the average soft error rate (SER) of the five circuits is reduced by 47.6%, the area is increased by 12.1%, and the power is increased by 31.5%.
{"title":"An Improved Multi-Objective Optimization Framework for Soft-Error Immune Circuits","authors":"Shaohang Chu, Yan Li, Xu Cheng, Xiaoyang Zeng","doi":"10.1109/APCCAS55924.2022.10090258","DOIUrl":"https://doi.org/10.1109/APCCAS55924.2022.10090258","url":null,"abstract":"Soft error is one of the main circuit reliability issues. Mitigating soft error inevitably requires sacrificing area and power, therefore, it is necessary to balance area, power, and soft error. In this paper, some improvements have been made to the multi-objective optimization framework based on Back Propagation (BP) neural network and Non-dominated Sorting Genetic Algorithm-II (NSGA-II). A data set selection and dimensionality reduction scheme is proposed to ensure that the framework is suitable for circuit designs of different scales. The experimental results show that the average soft error rate (SER) of the five circuits is reduced by 47.6%, the area is increased by 12.1%, and the power is increased by 31.5%.","PeriodicalId":243739,"journal":{"name":"2022 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115199227","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-11-11DOI: 10.1109/APCCAS55924.2022.10090401
Wending Qi, Anning Liu, Ruolin Zhou, Songping Mai
The next-generation of neural prostheses such as optogenetic cochlear implants (CIs) can be implemented by a 2FSK-based wireless power and data transfer (WPDT) system over a signal inductive link. Optimizing the power efficiency of the link is imperative to minimize the heating dissipation in tissue and interference with other devices. And to mimic natural auditory perception with high fidelity, data rate is also important. Previous design methodologies for coils are not comprehensive and accurate enough to account for data transmission and operation at dual carrier frequencies. We outline the theoretical foundation of optimal power transmission and compromise it with data transmission. We use this foundation to propose an iterative dual frequencies coils (DFC) design procedure for 2FSK-based WPDT system. Moreover, we execute this procedure at 3.951 and 4.516 MHz achieving power transfer efficiency (PTE) and power deliver to the load (PDL) of 77.4% and 230.25mW respectively, and the data rate reaches 564 Kbps, at 12mm spacing. All results are verified with simulations using MATLAB and measurements using helical coils fabricated on printed circuit boards.
{"title":"Design and Optimization of Inductive Coils for 2FSK-based Power and Data Transmission for Biomedical Implants","authors":"Wending Qi, Anning Liu, Ruolin Zhou, Songping Mai","doi":"10.1109/APCCAS55924.2022.10090401","DOIUrl":"https://doi.org/10.1109/APCCAS55924.2022.10090401","url":null,"abstract":"The next-generation of neural prostheses such as optogenetic cochlear implants (CIs) can be implemented by a 2FSK-based wireless power and data transfer (WPDT) system over a signal inductive link. Optimizing the power efficiency of the link is imperative to minimize the heating dissipation in tissue and interference with other devices. And to mimic natural auditory perception with high fidelity, data rate is also important. Previous design methodologies for coils are not comprehensive and accurate enough to account for data transmission and operation at dual carrier frequencies. We outline the theoretical foundation of optimal power transmission and compromise it with data transmission. We use this foundation to propose an iterative dual frequencies coils (DFC) design procedure for 2FSK-based WPDT system. Moreover, we execute this procedure at 3.951 and 4.516 MHz achieving power transfer efficiency (PTE) and power deliver to the load (PDL) of 77.4% and 230.25mW respectively, and the data rate reaches 564 Kbps, at 12mm spacing. All results are verified with simulations using MATLAB and measurements using helical coils fabricated on printed circuit boards.","PeriodicalId":243739,"journal":{"name":"2022 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"179 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116395507","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-11-11DOI: 10.1109/APCCAS55924.2022.10090370
Zhixiang Liu, Shiyou Wei, Gengzhen Qi, Pui-in Mak
This paper reports a self-interference-resilient receiver (RX) for 5G-NR-FDD covering 0.5 to 2GHz. It incorporates a $4^{text{th}}$-order gain-boosted N-path low-noise amplifier (LNA) and a $2^{text{nd}}$-order baseband (BB) TIA to widen the −3dB RF-BW and also enhance the out-of-band (OOB) roll-off slope. Furthermore, a positive-feedback loop is created for the input-impedance matching purpose thanks to the impedance-translation property of the N-path network. Implemented in 65nm CMOS process, the simulation results show that with >54MHz RF-BW the RX achieves >24dB OOB rejection at 80MHz offset. When the offset frequency $(Delta f)$ is twice the −3dB RF-BW, the RX achieves 32dBm OOB-IIP3, while consuming a reasonable power of 27 to 67mW. The noise figure (NF) ranges from 3.2 to 5.5dB and active area is $0.38text{mm}^{2}$.
{"title":"A 32dBm OOB-IIP3 BW-Extended 5G-NR Receiver with 4th-Order Gain-Boosted N-Path LNA","authors":"Zhixiang Liu, Shiyou Wei, Gengzhen Qi, Pui-in Mak","doi":"10.1109/APCCAS55924.2022.10090370","DOIUrl":"https://doi.org/10.1109/APCCAS55924.2022.10090370","url":null,"abstract":"This paper reports a self-interference-resilient receiver (RX) for 5G-NR-FDD covering 0.5 to 2GHz. It incorporates a $4^{text{th}}$-order gain-boosted N-path low-noise amplifier (LNA) and a $2^{text{nd}}$-order baseband (BB) TIA to widen the −3dB RF-BW and also enhance the out-of-band (OOB) roll-off slope. Furthermore, a positive-feedback loop is created for the input-impedance matching purpose thanks to the impedance-translation property of the N-path network. Implemented in 65nm CMOS process, the simulation results show that with >54MHz RF-BW the RX achieves >24dB OOB rejection at 80MHz offset. When the offset frequency $(Delta f)$ is twice the −3dB RF-BW, the RX achieves 32dBm OOB-IIP3, while consuming a reasonable power of 27 to 67mW. The noise figure (NF) ranges from 3.2 to 5.5dB and active area is $0.38text{mm}^{2}$.","PeriodicalId":243739,"journal":{"name":"2022 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122593073","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-11-11DOI: 10.1109/APCCAS55924.2022.10090266
Daiki Ogata, R. Kamiya, Yusuke Toyoshima, K. Ohhata
This paper proposes a high-time-resolution time to digital converter (TDC) using a coupled ring oscillator (CRO) with phase averaging. The CRO can generate short time interval multiphase clocks, and combining it with a counter enables a high-time-resolution TDC with a wide input range and relatively small circuitry. In addition, the application of phase averaging to the CRO reduces the timing error due to mismatch. A novel sampling technique is also proposed to eliminate the sampling error due to counter delay and glitches. Post-layout simulations were performed on a 10-bit TDC in 28-nm CMOS technology to evaluate the performance of the proposed TDC. The results showed that the high time resolution of 2.5 ps and low power dissipation of 15.6 m W at the sampling frequency of 350 MHz could be obtained, along with the FOM of 0.083 pJ/conv.-step.
本文提出了一种采用相位平均耦合环振荡器的高时间分辨率时数转换器(TDC)。CRO可以产生短时间间隔多相时钟，并与计数器相结合，使其具有宽输入范围和相对较小的电路的高时间分辨率TDC。此外，将相位平均应用于CRO，减小了由于失配引起的时序误差。提出了一种新的采样技术，以消除由于计数器延迟和小故障引起的采样误差。在28纳米CMOS技术的10位TDC上进行了布局后仿真，以评估所提出的TDC的性能。结果表明，在350 MHz的采样频率下，可获得2.5 ps的高时间分辨率和15.6 m W的低功耗，FOM为0.083 pJ/con .-step。
{"title":"A High-Time-Resolution Time-to-Digital Converter Using Coupled Ring Oscillator with Phase Averaging","authors":"Daiki Ogata, R. Kamiya, Yusuke Toyoshima, K. Ohhata","doi":"10.1109/APCCAS55924.2022.10090266","DOIUrl":"https://doi.org/10.1109/APCCAS55924.2022.10090266","url":null,"abstract":"This paper proposes a high-time-resolution time to digital converter (TDC) using a coupled ring oscillator (CRO) with phase averaging. The CRO can generate short time interval multiphase clocks, and combining it with a counter enables a high-time-resolution TDC with a wide input range and relatively small circuitry. In addition, the application of phase averaging to the CRO reduces the timing error due to mismatch. A novel sampling technique is also proposed to eliminate the sampling error due to counter delay and glitches. Post-layout simulations were performed on a 10-bit TDC in 28-nm CMOS technology to evaluate the performance of the proposed TDC. The results showed that the high time resolution of 2.5 ps and low power dissipation of 15.6 m W at the sampling frequency of 350 MHz could be obtained, along with the FOM of 0.083 pJ/conv.-step.","PeriodicalId":243739,"journal":{"name":"2022 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"529 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114518810","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-11-11DOI: 10.1109/APCCAS55924.2022.10090353
R. Kumar, Divyanshu Divyanshu, Danial Khan, S. Amara, Y. Massoud
This work explores spin-orbit torque (SOT) assisted magnetic tunnel junction (MTJ) as a potential candidate for designing sneaky hardware Trojan (HT). The type of payload targeted is IC malfunction using an externally triggered activation mechanism with an external magnetic field. To make it sneakier, we designed the Trojan to have sufficient tolerance to stray magnetic fields and thermal stability to ensure better-hidden operation for temperature-based tests during system-on-a-chip (SoC) flow. For creating a smaller Trojan, the energy barrier height's effect must be considered. Therefore, an appropriate optimization for SOT-assisted MTJ is required. This work thus considers the effect of process variation in key MTJ parameters by using Monte-Carlo (MC) simulations, and the effect of temperature sweep is utilized to determine the operational ability of the Trojan. We also conclude the Trojan optimization design by analysing its behaviour for high-speed IC operation by performing eye-diagram tests and transient analysis measurements for more practical applications. This work shows that a 5% reduction in MTJ key dimensions for Trojan operation has around 58.87% reduction in the critical magnetic field required for triggering with sufficient tolerance to process variation. Thus, this work contributes towards optimization of hardware Trojan for more sneaky operation.
{"title":"Modeling of Sneaky Hardware Trojan Using Spin-orbit Torque Assisted Magnetic Tunnel Junction for High Speed Digital Circuits","authors":"R. Kumar, Divyanshu Divyanshu, Danial Khan, S. Amara, Y. Massoud","doi":"10.1109/APCCAS55924.2022.10090353","DOIUrl":"https://doi.org/10.1109/APCCAS55924.2022.10090353","url":null,"abstract":"This work explores spin-orbit torque (SOT) assisted magnetic tunnel junction (MTJ) as a potential candidate for designing sneaky hardware Trojan (HT). The type of payload targeted is IC malfunction using an externally triggered activation mechanism with an external magnetic field. To make it sneakier, we designed the Trojan to have sufficient tolerance to stray magnetic fields and thermal stability to ensure better-hidden operation for temperature-based tests during system-on-a-chip (SoC) flow. For creating a smaller Trojan, the energy barrier height's effect must be considered. Therefore, an appropriate optimization for SOT-assisted MTJ is required. This work thus considers the effect of process variation in key MTJ parameters by using Monte-Carlo (MC) simulations, and the effect of temperature sweep is utilized to determine the operational ability of the Trojan. We also conclude the Trojan optimization design by analysing its behaviour for high-speed IC operation by performing eye-diagram tests and transient analysis measurements for more practical applications. This work shows that a 5% reduction in MTJ key dimensions for Trojan operation has around 58.87% reduction in the critical magnetic field required for triggering with sufficient tolerance to process variation. Thus, this work contributes towards optimization of hardware Trojan for more sneaky operation.","PeriodicalId":243739,"journal":{"name":"2022 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129716617","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-11-11DOI: 10.1109/APCCAS55924.2022.10090399
Langtao Chen, Xin Zhou, Ying Wang, Ying Kong, R. Xie, Ling Peng, Yantu Mo, M. Qiao, Bo Zhang
In this paper, single event burnout (SEB) effect is investigated for 18V Lateral-diffused MOS (LDMOS) based on 0.18µm process technology. The SEB mechanism is revealed that parasitic bipolar turn-on and the self-maintaining induced by avalanche ionization. At early stage, heavy ion induced ionized holes inject into the P-body (PB) region, giving rise to the parasitic bipolar turn-on. Electrons from the source are allowed to flow to the drain, and exert modulation on electric field profile. Due to field peak formed at drain side, avalanche ionization induced holes provide a supplement for base current of the parasitic bipolar. A positive feedback of holes between the parasitic bipolar and avalanche is responsible for the SEB effect. Multi-implantation radiation hardening technology is proposed to reduce PB region resistance and suppress parasitic bipolar opened, while eliminate the impact on threshold voltage.
{"title":"Study on Single Event Burnout Effect for 18V LDMOS Based on 0.18µm Process Technology","authors":"Langtao Chen, Xin Zhou, Ying Wang, Ying Kong, R. Xie, Ling Peng, Yantu Mo, M. Qiao, Bo Zhang","doi":"10.1109/APCCAS55924.2022.10090399","DOIUrl":"https://doi.org/10.1109/APCCAS55924.2022.10090399","url":null,"abstract":"In this paper, single event burnout (SEB) effect is investigated for 18V Lateral-diffused MOS (LDMOS) based on 0.18µm process technology. The SEB mechanism is revealed that parasitic bipolar turn-on and the self-maintaining induced by avalanche ionization. At early stage, heavy ion induced ionized holes inject into the P-body (PB) region, giving rise to the parasitic bipolar turn-on. Electrons from the source are allowed to flow to the drain, and exert modulation on electric field profile. Due to field peak formed at drain side, avalanche ionization induced holes provide a supplement for base current of the parasitic bipolar. A positive feedback of holes between the parasitic bipolar and avalanche is responsible for the SEB effect. Multi-implantation radiation hardening technology is proposed to reduce PB region resistance and suppress parasitic bipolar opened, while eliminate the impact on threshold voltage.","PeriodicalId":243739,"journal":{"name":"2022 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128983756","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-11-11DOI: 10.1109/APCCAS55924.2022.10090385
Xinyuan Qiao, Keyue Deng, Yuxing Chen, Suwen Song, Zhongfeng Wang
The long binary Bose-Chaudhuri-Hochquenghem (BCH) codes are widely used in communication and storage systems, and massive-parallel BCH decoders are expected to satisfy the requirement of high throughput. However, a large parallel degree leads to a significant increase in the hardware complexity of the syndrome computation (SC) module. Considering the similarities between SC and discrete Fourier transform (DFT), this paper proposes an advanced cyclotomic fast Fourier transform (CFFT) algorithm-aided SC architecture, which fully utilizes the property of characteristic-2 fields of binary BCH codes to reduce hardware complexity. The implementation results show that the proposed CFFT-aided architecture is desirable for long binary BCH codes with the error-correction capability less than 20. For (16383, 16271, 8) BCH code over GF(214), the hardware overhead of a 128-parallel SC module is reduced by 16% compared to the state-of-the-art architecture.
{"title":"Low-Complexity Parallel Syndrome Computation for BCH Decoders Based on Cyclotomic FFT","authors":"Xinyuan Qiao, Keyue Deng, Yuxing Chen, Suwen Song, Zhongfeng Wang","doi":"10.1109/APCCAS55924.2022.10090385","DOIUrl":"https://doi.org/10.1109/APCCAS55924.2022.10090385","url":null,"abstract":"The long binary Bose-Chaudhuri-Hochquenghem (BCH) codes are widely used in communication and storage systems, and massive-parallel BCH decoders are expected to satisfy the requirement of high throughput. However, a large parallel degree leads to a significant increase in the hardware complexity of the syndrome computation (SC) module. Considering the similarities between SC and discrete Fourier transform (DFT), this paper proposes an advanced cyclotomic fast Fourier transform (CFFT) algorithm-aided SC architecture, which fully utilizes the property of characteristic-2 fields of binary BCH codes to reduce hardware complexity. The implementation results show that the proposed CFFT-aided architecture is desirable for long binary BCH codes with the error-correction capability less than 20. For (16383, 16271, 8) BCH code over GF(214), the hardware overhead of a 128-parallel SC module is reduced by 16% compared to the state-of-the-art architecture.","PeriodicalId":243739,"journal":{"name":"2022 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121330400","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper presents a low-power and low-noise front-end amplifier (FEA) dedicated to recording and preprocessing biomedical signals for brain-machine interface. The FEA employs a current-reused architecture which adopts an inverter-based differential input stage to achieve considerable $g_{m}/I$ efficiency and low noise. With a carefully designed common-mode feedback circuit, the output common-mode voltage of the fully-differential FEA is stabilized within an acceptable margin of error about 1 mV. All transistors in FEA operate in the sub-threshold region, realizing low power consumption. This current-reused FEA implemented in a CMOS 0.18- $mu mathbf{m}$ technology provides a noise efficiency factor (NEF) and power efficiency factor (PEF) of 1.6 and 2.56, respectively, corresponding to an input-referred noise of 2.37 $mu boldsymbol{V}_{rms}$. This FEA consumes only 2 $mu mathbf{A}$ current from 1 V supply and the active area is $0.2 mathbf{mm} times 0.2$ mm.
{"title":"A Low-Noise Neural Signal Amplifier Achieving 1.6 NEF and 2.56 PEF for Brain-Machine Interface","authors":"Weijian Chen, Xu Liu, Weisong Liang, Ze-Xi Lu, Peiyuan Wan, Zhijie Chen","doi":"10.1109/APCCAS55924.2022.10090394","DOIUrl":"https://doi.org/10.1109/APCCAS55924.2022.10090394","url":null,"abstract":"This paper presents a low-power and low-noise front-end amplifier (FEA) dedicated to recording and preprocessing biomedical signals for brain-machine interface. The FEA employs a current-reused architecture which adopts an inverter-based differential input stage to achieve considerable $g_{m}/I$ efficiency and low noise. With a carefully designed common-mode feedback circuit, the output common-mode voltage of the fully-differential FEA is stabilized within an acceptable margin of error about 1 mV. All transistors in FEA operate in the sub-threshold region, realizing low power consumption. This current-reused FEA implemented in a CMOS 0.18- $mu mathbf{m}$ technology provides a noise efficiency factor (NEF) and power efficiency factor (PEF) of 1.6 and 2.56, respectively, corresponding to an input-referred noise of 2.37 $mu boldsymbol{V}_{rms}$. This FEA consumes only 2 $mu mathbf{A}$ current from 1 V supply and the active area is $0.2 mathbf{mm} times 0.2$ mm.","PeriodicalId":243739,"journal":{"name":"2022 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130884540","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-11-11DOI: 10.1109/APCCAS55924.2022.10090274
Mohamed Karaa, Hakim Ghazzai, Lokman Sboui, Hichem Besbes, Y. Massoud
Road surface condition estimation plays a crucial role in road safety and maintenance, especially in adverse weather conditions like snowfall. In this paper, we introduce a framework for unsupervised annotation of a dataset describing road snow cover level. This framework relies on feature learning using autoencoders and graph clustering using the Louvain community detection algorithm. We also incorporate time and weather data to facilitate the annotation process. We evaluate our method by assessing its different steps and comparing it to another density-based clustering method. We also present a large image dataset describing four road cover states in urban scenes, including different weather and visual conditions. The dataset comprises 41346 images collected from road monitoring cameras installed in Montreal, Canada, during the 2022 winter season. This dataset intends to help integrate computer vision techniques in planning snow removal operations.
{"title":"Unsupervised Image Dataset Annotation Framework for Snow Covered Road Networks","authors":"Mohamed Karaa, Hakim Ghazzai, Lokman Sboui, Hichem Besbes, Y. Massoud","doi":"10.1109/APCCAS55924.2022.10090274","DOIUrl":"https://doi.org/10.1109/APCCAS55924.2022.10090274","url":null,"abstract":"Road surface condition estimation plays a crucial role in road safety and maintenance, especially in adverse weather conditions like snowfall. In this paper, we introduce a framework for unsupervised annotation of a dataset describing road snow cover level. This framework relies on feature learning using autoencoders and graph clustering using the Louvain community detection algorithm. We also incorporate time and weather data to facilitate the annotation process. We evaluate our method by assessing its different steps and comparing it to another density-based clustering method. We also present a large image dataset describing four road cover states in urban scenes, including different weather and visual conditions. The dataset comprises 41346 images collected from road monitoring cameras installed in Montreal, Canada, during the 2022 winter season. This dataset intends to help integrate computer vision techniques in planning snow removal operations.","PeriodicalId":243739,"journal":{"name":"2022 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115765283","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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