A fine-grained co-simulation methodology for IR-drop noise in silicon interposer and TSV-based 3D IC

Abstract

In this paper, we propose a methodology which can co-simulate IR-drop noise for 3D IC, silicon interposer, and PCB simultaneously, and demonstrate how severe the IR-drop is in the silicon interposer. This methodology uses not only PCB and package (silicon interposer) stacking information, but also full transistor-level 3D IC switching information for a precise IR-drop calculation. By utilizing these information, we show the IR-drop noise map of the PDN (Power Distribution Network) in the interposer and the 3D IC mounted on it. Based on our results, we found that (1) the IR-drop noise caused by silicon interposer is very severe to few tens of mV, and (2) our co-analysis method fixes the overestimation of IR-drop caused by the traditional method.