ESD protection in fully-depleted CMOS/SIMOX with a tungsten-clad source/drain

Abstract

The effect of a tungsten (W) clad source/drain on the electrostatic discharge (ESD) protection in fully-depleted CMOS/SIMOX devices was studied. The ESD failure voltage based on the human-body model (HBM) in a CMOS input circuit was measured for three types of clad W-layer layouts. High ESD immunity of 4000 V was obtained for the fully-W-clad layout when the threshold voltage was less than 0.24 V and the threshold voltage dependence was observed. The blocked layout of the clad W layer provided an ESD protection level of over 3500 V at varied threshold voltages. A gapped W-layer layout provided 3000 V level immunity while keeping the resistance of the gate electrode low for high-speed operation in the output buffer. Based on these results, an optimized layout for the W layer in fully-depleted SOI technology is presented.