Pub Date : 2000-09-26DOI: 10.1109/EOSESD.2000.890103
B. Unger
Static charges can develop on devices with movement in shipping packages. During subsequent handling or testing operations, an ESD (electrostatic discharge) can result in device failure. Therefore, the materials used to package semiconductor devices should be selected for their ability to minimize charging and damaging ESDs. Some triboelectric charging test results are shown that suggest that some of these device packages contribute to the failure rate at the assembly facilities.
{"title":"Device charging in shipping packages","authors":"B. Unger","doi":"10.1109/EOSESD.2000.890103","DOIUrl":"https://doi.org/10.1109/EOSESD.2000.890103","url":null,"abstract":"Static charges can develop on devices with movement in shipping packages. During subsequent handling or testing operations, an ESD (electrostatic discharge) can result in device failure. Therefore, the materials used to package semiconductor devices should be selected for their ability to minimize charging and damaging ESDs. Some triboelectric charging test results are shown that suggest that some of these device packages contribute to the failure rate at the assembly facilities.","PeriodicalId":332394,"journal":{"name":"Electrical Overstress/Electrostatic Discharge Symposium Proceedings 2000 (IEEE Cat. No.00TH8476)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2000-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122745337","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-09-26DOI: 10.1109/EOSESD.2000.890084
C. Richier, Pascal Salome, G. Mabboux, I. Zaza, A. Juge, P. Mortini
ESD protection for RF applications must deal with good ESD performance, minimum capacitance, zero series resistance and good capacitance linearity. In order to fulfil these requirements, different ESD protection strategies for RF applications have been investigated in a 0.18 /spl mu/m CMOS process. This paper compares different ESD protection devices and shows that a suitable ESD performance target for RF applications (200 fF max, 2 kV HBM) can be reached with a diode network scheme. The optimization of the diodes is then a key point which is detailed. A trade-off must be found between the ESD performance, the voltage drop during ESD and the parasitic capacitance. Poly as well as STI bounded diodes have been studied and it appears clearly that a solution based on poly bounded diodes is the best choice.
{"title":"Investigation on different ESD protection strategies devoted to 3.3 V RF applications (2 GHz) in a 0.18 /spl mu/m CMOS process","authors":"C. Richier, Pascal Salome, G. Mabboux, I. Zaza, A. Juge, P. Mortini","doi":"10.1109/EOSESD.2000.890084","DOIUrl":"https://doi.org/10.1109/EOSESD.2000.890084","url":null,"abstract":"ESD protection for RF applications must deal with good ESD performance, minimum capacitance, zero series resistance and good capacitance linearity. In order to fulfil these requirements, different ESD protection strategies for RF applications have been investigated in a 0.18 /spl mu/m CMOS process. This paper compares different ESD protection devices and shows that a suitable ESD performance target for RF applications (200 fF max, 2 kV HBM) can be reached with a diode network scheme. The optimization of the diodes is then a key point which is detailed. A trade-off must be found between the ESD performance, the voltage drop during ESD and the parasitic capacitance. Poly as well as STI bounded diodes have been studied and it appears clearly that a solution based on poly bounded diodes is the best choice.","PeriodicalId":332394,"journal":{"name":"Electrical Overstress/Electrostatic Discharge Symposium Proceedings 2000 (IEEE Cat. No.00TH8476)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2000-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129619177","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-09-26DOI: 10.1109/EOSESD.2000.890032
J.C. Lee, M. A. Hoque, G. Croft, J. Liou, W. R. Young, J. Bernier
Electrostatic discharge (ESD) is responsible for more than 25% of semiconductor device and chip damage each year. This paper focuses on an ESD event resulting from the charge being transferred from a human body to an integrated circuit (i.e. the human body model, HBM). In particular, the study provides simulation and experimental results to determine the main mechanism governing the failure of MOS devices subjected to the HBM stress. Based on this mechanism, the correct pulse needed to measure the HBM ESD characteristics using the transmission line pulse (TLP) technique is also determined and recommended.
{"title":"A method for determining a transmission line pulse shape that produces equivalent results to human body model testing methods","authors":"J.C. Lee, M. A. Hoque, G. Croft, J. Liou, W. R. Young, J. Bernier","doi":"10.1109/EOSESD.2000.890032","DOIUrl":"https://doi.org/10.1109/EOSESD.2000.890032","url":null,"abstract":"Electrostatic discharge (ESD) is responsible for more than 25% of semiconductor device and chip damage each year. This paper focuses on an ESD event resulting from the charge being transferred from a human body to an integrated circuit (i.e. the human body model, HBM). In particular, the study provides simulation and experimental results to determine the main mechanism governing the failure of MOS devices subjected to the HBM stress. Based on this mechanism, the correct pulse needed to measure the HBM ESD characteristics using the transmission line pulse (TLP) technique is also determined and recommended.","PeriodicalId":332394,"journal":{"name":"Electrical Overstress/Electrostatic Discharge Symposium Proceedings 2000 (IEEE Cat. No.00TH8476)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2000-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129057686","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
We have proposed a simple analytical model for the N-well resistor up to the turnover point in the I-V characteristic of the device. A simple and accurate method of extraction of the parameters used on which this model is based has also been proposed. Furthermore, the scalability of these parameters has also been studied. The model and its scalability have been verified with experimental data.
{"title":"A scalable analytical model for the ESD N-well resistor","authors":"Venugopal Puvvada, Venkatesh Srinivasan, Vishal Gupta","doi":"10.1109/EOSESD.2000.890113","DOIUrl":"https://doi.org/10.1109/EOSESD.2000.890113","url":null,"abstract":"We have proposed a simple analytical model for the N-well resistor up to the turnover point in the I-V characteristic of the device. A simple and accurate method of extraction of the parameters used on which this model is based has also been proposed. Furthermore, the scalability of these parameters has also been studied. The model and its scalability have been verified with experimental data.","PeriodicalId":332394,"journal":{"name":"Electrical Overstress/Electrostatic Discharge Symposium Proceedings 2000 (IEEE Cat. No.00TH8476)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2000-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121580266","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-09-26DOI: 10.1109/EOSESD.2000.890036
K.J. Kim, M. Hardwick, H. Pham, T. Fahey
A new class of inherently dissipative polymer (IDP) alloys has been developed through recent advances in IDP formulation utilizing additional charge carriers in the polymerization of the IDP. This new generation of IDP technology delivers static decay times of less than 0.1 s and surface resistance values of 10/sup 7/ /spl Omega/ which are two orders of magnitude better than previously available generations of IDPs. This IDP technology has enabled the development of a new class of IDP alloys with host polymers such as PETG, polypropylene and polyurethane. These IDP alloys reach previously unattainable surface and volume resistance levels of 10/sup 8/ /spl Omega/. These resistance values hold permanently and consistently through injection molding or extrusion due to a flat loading curve, differing from the steep loading curves in this resistance range seen in conductive filler systems. Additional optimization of the IDP alloys has led to improvements in cleanliness. Packaging and components therefore exhibit consistent, permanent surface resistance values between 10/sup 8/ and 10/sup 9/ /spl Omega/ without introducing contaminants into the cleanroom. The new class of IDP alloys provides new levels of clean, consistent ESD protection via a unique blend of electrical, physical, and cleanliness properties of the optimized alloy.
{"title":"Advancements in inherently dissipative polymer (IDP) alloys provide new levels of clean, consistent ESD protection","authors":"K.J. Kim, M. Hardwick, H. Pham, T. Fahey","doi":"10.1109/EOSESD.2000.890036","DOIUrl":"https://doi.org/10.1109/EOSESD.2000.890036","url":null,"abstract":"A new class of inherently dissipative polymer (IDP) alloys has been developed through recent advances in IDP formulation utilizing additional charge carriers in the polymerization of the IDP. This new generation of IDP technology delivers static decay times of less than 0.1 s and surface resistance values of 10/sup 7/ /spl Omega/ which are two orders of magnitude better than previously available generations of IDPs. This IDP technology has enabled the development of a new class of IDP alloys with host polymers such as PETG, polypropylene and polyurethane. These IDP alloys reach previously unattainable surface and volume resistance levels of 10/sup 8/ /spl Omega/. These resistance values hold permanently and consistently through injection molding or extrusion due to a flat loading curve, differing from the steep loading curves in this resistance range seen in conductive filler systems. Additional optimization of the IDP alloys has led to improvements in cleanliness. Packaging and components therefore exhibit consistent, permanent surface resistance values between 10/sup 8/ and 10/sup 9/ /spl Omega/ without introducing contaminants into the cleanroom. The new class of IDP alloys provides new levels of clean, consistent ESD protection via a unique blend of electrical, physical, and cleanliness properties of the optimized alloy.","PeriodicalId":332394,"journal":{"name":"Electrical Overstress/Electrostatic Discharge Symposium Proceedings 2000 (IEEE Cat. No.00TH8476)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2000-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127553979","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-09-26DOI: 10.1109/EOSESD.2000.890029
T. Brodbeck
The standards for testing the ESD sensitivity of electronic components according to the HBM (MIL, JEDEC, ESDA) require a specific switch in the HBM ESD waveform generator to ensure that the socket and the DUT is not left in a charged state after the stress. The absence of this switch may result in the wrong ESD threshold levels. For two different waveform generators, the charging effect was measured by using an electrostatic voltmeter. An unexpected experimental result, showing that the HBM ESD threshold voltage strongly depends on the number of stress pulses, could be explained by the measured charging of these components. Consequences for other types of components and corrective actions are discussed.
{"title":"Influence of the charging effect on HBM ESD device testing","authors":"T. Brodbeck","doi":"10.1109/EOSESD.2000.890029","DOIUrl":"https://doi.org/10.1109/EOSESD.2000.890029","url":null,"abstract":"The standards for testing the ESD sensitivity of electronic components according to the HBM (MIL, JEDEC, ESDA) require a specific switch in the HBM ESD waveform generator to ensure that the socket and the DUT is not left in a charged state after the stress. The absence of this switch may result in the wrong ESD threshold levels. For two different waveform generators, the charging effect was measured by using an electrostatic voltmeter. An unexpected experimental result, showing that the HBM ESD threshold voltage strongly depends on the number of stress pulses, could be explained by the measured charging of these components. Consequences for other types of components and corrective actions are discussed.","PeriodicalId":332394,"journal":{"name":"Electrical Overstress/Electrostatic Discharge Symposium Proceedings 2000 (IEEE Cat. No.00TH8476)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2000-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117295746","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-09-26DOI: 10.1109/EOSESD.2000.890117
M. Baird, R. Ida
For many classes of technologies and circuits, it is beneficial to perform circuit simulations for ESD design, verification, and performance prediction. This is particularly true for mixed-signal ICs, where complex interaction between I/Os and multiple power supplies make manual analysis difficult and error prone. Unfortunately, high node and component counts typically prohibit simulations of an entire circuit. Thus, a manual intervention by the designer is usually required to minimize the circuit size. This paper introduces a new tool which automatically reduces the number of voltage nodes per ESD simulation by including only those devices that are necessary. In addition, a simple method for modeling ESD device failure while maintaining compatibility with existing CAD tools and libraries is discussed.
{"title":"VerifyESD: a tool for efficient circuit level ESD simulations of mixed-signal ICs","authors":"M. Baird, R. Ida","doi":"10.1109/EOSESD.2000.890117","DOIUrl":"https://doi.org/10.1109/EOSESD.2000.890117","url":null,"abstract":"For many classes of technologies and circuits, it is beneficial to perform circuit simulations for ESD design, verification, and performance prediction. This is particularly true for mixed-signal ICs, where complex interaction between I/Os and multiple power supplies make manual analysis difficult and error prone. Unfortunately, high node and component counts typically prohibit simulations of an entire circuit. Thus, a manual intervention by the designer is usually required to minimize the circuit size. This paper introduces a new tool which automatically reduces the number of voltage nodes per ESD simulation by including only those devices that are necessary. In addition, a simple method for modeling ESD device failure while maintaining compatibility with existing CAD tools and libraries is discussed.","PeriodicalId":332394,"journal":{"name":"Electrical Overstress/Electrostatic Discharge Symposium Proceedings 2000 (IEEE Cat. No.00TH8476)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2000-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131040553","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Reticles were exposed to the fringing field from an electrode biased to a high voltage. The reticles in the study included special reticles intended to benchmark the ESD hazard of a photobay and production reticles of a variety of feature sizes. It was found that without any electrical contact between the reticle and the electrode, reticle damage could be done. A wide bandwidth transient-EMI sensing antenna revealed that the reticle sparked when a voltage as low as 2000 V was applied to the electrode. The tests showed that the ESD threshold of reticles with smaller feature sizes was lower than for reticles with larger feature sizes. Reticles were scanned under a microscope for reticle damage. It was found that when the voltage was ramped to 17 kV and returned to zero, damage to the reticle was observed. When a voltage of 7.5 kV was applied once, no damage was observed but when it was applied 100 times, reticle damage was observed. This study confirms that ESD damage is done to a reticle by charged objects in the vicinity of the reticle in contrast with the prevailing belief that reticle damage is done only by charged reticles. The study also showed that reticles can be sufficiently damaged to cause printing errors due to the accumulated damage caused by repeated low level exposure to the fringing field of a charged object in the vicinity of the reticle.
{"title":"A study of the mechanisms for ESD damage to reticles","authors":"J. Montoya, L. Levit, A. Englisch","doi":"10.1109/6104.930957","DOIUrl":"https://doi.org/10.1109/6104.930957","url":null,"abstract":"Reticles were exposed to the fringing field from an electrode biased to a high voltage. The reticles in the study included special reticles intended to benchmark the ESD hazard of a photobay and production reticles of a variety of feature sizes. It was found that without any electrical contact between the reticle and the electrode, reticle damage could be done. A wide bandwidth transient-EMI sensing antenna revealed that the reticle sparked when a voltage as low as 2000 V was applied to the electrode. The tests showed that the ESD threshold of reticles with smaller feature sizes was lower than for reticles with larger feature sizes. Reticles were scanned under a microscope for reticle damage. It was found that when the voltage was ramped to 17 kV and returned to zero, damage to the reticle was observed. When a voltage of 7.5 kV was applied once, no damage was observed but when it was applied 100 times, reticle damage was observed. This study confirms that ESD damage is done to a reticle by charged objects in the vicinity of the reticle in contrast with the prevailing belief that reticle damage is done only by charged reticles. The study also showed that reticles can be sufficiently damaged to cause printing errors due to the accumulated damage caused by repeated low level exposure to the fringing field of a charged object in the vicinity of the reticle.","PeriodicalId":332394,"journal":{"name":"Electrical Overstress/Electrostatic Discharge Symposium Proceedings 2000 (IEEE Cat. No.00TH8476)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2000-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115078757","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-09-26DOI: 10.1109/EOSESD.2000.890035
R. Rosner
Plastic resins, because of their low cost, versatility and ease of use, play an important role in many static control applications including packaging and work surfaces. A wide range of properties may be realized with plastics depending on the selection of the resin, filler or additive. This paper seeks to explain how these properties come about based on the chemical structure of the polymers. It also reviews the various way of imparting electrical conductivity on plastic resins through the use of antistatic agents, conductive fillers and intrinsically conductive polymers.
{"title":"Conductive materials for ESD applications: an overview","authors":"R. Rosner","doi":"10.1109/EOSESD.2000.890035","DOIUrl":"https://doi.org/10.1109/EOSESD.2000.890035","url":null,"abstract":"Plastic resins, because of their low cost, versatility and ease of use, play an important role in many static control applications including packaging and work surfaces. A wide range of properties may be realized with plastics depending on the selection of the resin, filler or additive. This paper seeks to explain how these properties come about based on the chemical structure of the polymers. It also reviews the various way of imparting electrical conductivity on plastic resins through the use of antistatic agents, conductive fillers and intrinsically conductive polymers.","PeriodicalId":332394,"journal":{"name":"Electrical Overstress/Electrostatic Discharge Symposium Proceedings 2000 (IEEE Cat. No.00TH8476)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2000-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116323370","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-09-26DOI: 10.1109/EOSESD.2000.890047
D. Nordin
The drive-level electrostatic discharge (ESD) behavior of a recent model of a desktop disk drive is discussed. ESD events are simulated up to 30 kV using an ESD gun (IEC-801). The drives were evaluated at the final assembly level. The head disk assemblies (HDAs) were equipped with GMR heads and single ended preamplifiers. In a manner similar to evaluations of head stack assemblies (Wallash, 1999), the head disk assemblies were stressed using an ESD gun at various strategic points of the drive. The printed circuit boards were in place when directing ESD events to the base and removed to address the motor pins. A quasi-static tester (QST) was employed to evaluate the GMR head condition as described by the signal amplitude, resistance and pinned layer orientation. The QST was able to evaluate the GMR condition without any disassembly of the drive. Analyses of the GMR condition before and after ESD stress are discussed.
{"title":"HDA-level ESD testing of giant magnetoresistive (GMR) recording heads","authors":"D. Nordin","doi":"10.1109/EOSESD.2000.890047","DOIUrl":"https://doi.org/10.1109/EOSESD.2000.890047","url":null,"abstract":"The drive-level electrostatic discharge (ESD) behavior of a recent model of a desktop disk drive is discussed. ESD events are simulated up to 30 kV using an ESD gun (IEC-801). The drives were evaluated at the final assembly level. The head disk assemblies (HDAs) were equipped with GMR heads and single ended preamplifiers. In a manner similar to evaluations of head stack assemblies (Wallash, 1999), the head disk assemblies were stressed using an ESD gun at various strategic points of the drive. The printed circuit boards were in place when directing ESD events to the base and removed to address the motor pins. A quasi-static tester (QST) was employed to evaluate the GMR head condition as described by the signal amplitude, resistance and pinned layer orientation. The QST was able to evaluate the GMR condition without any disassembly of the drive. Analyses of the GMR condition before and after ESD stress are discussed.","PeriodicalId":332394,"journal":{"name":"Electrical Overstress/Electrostatic Discharge Symposium Proceedings 2000 (IEEE Cat. No.00TH8476)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2000-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116853474","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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