W. Liu, Z. Liu, Y. Luo, G. Jiao, X. Huang, D. Huang, C. Liao, L. Zhang, Z. Gan, W. Wong, Ming-Fu Li
{"title":"Characteristics of NBTI in pMOSFETs with thermally and plasma nitrided gate oxides","authors":"W. Liu, Z. Liu, Y. Luo, G. Jiao, X. Huang, D. Huang, C. Liao, L. Zhang, Z. Gan, W. Wong, Ming-Fu Li","doi":"10.1109/ICSICT.2008.4734614","DOIUrl":null,"url":null,"abstract":"Negative bias temperature instability in pMOSFETs with thermally and plasma nitrided oxides is investigated using quasi-DC Id-Vg (slow Id-Vg) and on-the-fly interface trap (OFIT) measurement methods. By comparing the OFIT results with those observed from Id-Vg measurements, we found that the threshold voltage shift measured by slow Id-Vg is mainly due to the interface trap since the oxide charge is essentially detrapped during the measurement delay. Quantitatively, the interface trap density measured by OFIT method is higher than that by slow Id-Vg measurement, since the latter measurement is subjected to the recovery effect. For the thermally and plasma nitrided oxides, we found the interface trap density is higher for thermally nitride oxide. However, the power law time exponent n as stress time is the same for the pMOSFETs with both processes.","PeriodicalId":436457,"journal":{"name":"2008 9th International Conference on Solid-State and Integrated-Circuit Technology","volume":"75 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2008-12-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2008 9th International Conference on Solid-State and Integrated-Circuit Technology","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICSICT.2008.4734614","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
Negative bias temperature instability in pMOSFETs with thermally and plasma nitrided oxides is investigated using quasi-DC Id-Vg (slow Id-Vg) and on-the-fly interface trap (OFIT) measurement methods. By comparing the OFIT results with those observed from Id-Vg measurements, we found that the threshold voltage shift measured by slow Id-Vg is mainly due to the interface trap since the oxide charge is essentially detrapped during the measurement delay. Quantitatively, the interface trap density measured by OFIT method is higher than that by slow Id-Vg measurement, since the latter measurement is subjected to the recovery effect. For the thermally and plasma nitrided oxides, we found the interface trap density is higher for thermally nitride oxide. However, the power law time exponent n as stress time is the same for the pMOSFETs with both processes.