H. Tseng, M. Ramón, L. Hebert, P. Tobin, D. Triyoso, J. Grant, Z.X. Jiang, D. Roan, S. Samavedam, D. Gilmer, S. Kalpat, C. Hobbs, W. Taylor, O. Adetutu, B. White
{"title":"ALD HfO/sub 2/ using heavy water (D/sub 2/O) for improved MOSFET stability","authors":"H. Tseng, M. Ramón, L. Hebert, P. Tobin, D. Triyoso, J. Grant, Z.X. Jiang, D. Roan, S. Samavedam, D. Gilmer, S. Kalpat, C. Hobbs, W. Taylor, O. Adetutu, B. White","doi":"10.1109/IEDM.2003.1269171","DOIUrl":null,"url":null,"abstract":"Device instability is one of the most challenging issues to implement high-k gate dielectrics. Incorporation of deuterium during the ALD (atomic layer deposition) process effectively improves the interface quality that enhances high-k device stability and reliability. Compared to H/sub 2/O processed HfO/sub 2/ devices, devices with D/sub 2/O processing result in a significantly smaller Vt shift after constant voltage stressing at room temperature and at 125/spl deg/C under NBTI/PBTI conditions, as well as a longer CHCI lifetime. This process is independent of transistor process integration and is relatively low cost. It has the potential to become an industry standard if ALD high-k gate dielectric processing is the final choice.","PeriodicalId":344286,"journal":{"name":"IEEE International Electron Devices Meeting 2003","volume":"37 6 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"8","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE International Electron Devices Meeting 2003","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IEDM.2003.1269171","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 8
Abstract
Device instability is one of the most challenging issues to implement high-k gate dielectrics. Incorporation of deuterium during the ALD (atomic layer deposition) process effectively improves the interface quality that enhances high-k device stability and reliability. Compared to H/sub 2/O processed HfO/sub 2/ devices, devices with D/sub 2/O processing result in a significantly smaller Vt shift after constant voltage stressing at room temperature and at 125/spl deg/C under NBTI/PBTI conditions, as well as a longer CHCI lifetime. This process is independent of transistor process integration and is relatively low cost. It has the potential to become an industry standard if ALD high-k gate dielectric processing is the final choice.
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