A Novel SONOS Structure For Nonvolatile Memories With Improved Data Retention

Reisinger, Franosch, Bohm
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This is why the actual use of SONOS memories is limited to military applications needing a high radiation hardness /U. The purpose of this work is to introduce for the first time a SONOS structure with write and erase times as short as for conventional SONOS memories but with a more than 8 orders of magnitude improvement in data retention time. This is achieved with only two minor modifications of the conventional SONOS EEPROM manufacturing process. Sample Preparation Our samples were prepared by implementing an ONO storage layer (shown in the inset of fig. 3) into a standard CMOS process. The two differences to conventional SONOS memories are a 308, G e l oxide (instead of 2 0 4 and a p'-doped (with Boron) polysilicon gate instead of the standard n'-doped gate. For reference purposes the same samples with n+-gates were also prepared. For the measurements n-channel FETs as well as large area MOS diodes were used. Basic Idea The idea is explained in fig. 2: The dominant charge loss mechanism is tunneling of charge from the nitride across the tunnel oxide to the substrate / 2 / . An increase in tunnel oxide thickness from 20A to 30A will increase the data retention time by several orders of magnitude. However, inreasing the tunnel oxide thickness increases the erase time because the tunneling probability for holes from the substrate into the nitride decreases also. Increasing the field to speed up the erasing does not help because the competing process Fowler Nordheim injection of electrons from the gate prevents a total discharge of trapped negative charge (see the erase-characteristics for n' gates in fig.5). A conventional SONOS EEPROM needs, as a built-in assymetry, the tunnel oxide to be thinner than the blocking oxide in order to keep the FN current smaller than the dwect tunneling current of holes. Note that this works at low fields only. In contrast our approach makes the tunnel oxide thick and suppresses the FN current from the conduction band of the gate by instead reducing the electron density in the gate. A precondition for this concept to work is an acceptor concentration of more than 1020cm'3 in order to prevent any n-inversion or band bending due to depletion for fields as high as 10MVkm. Results and discussion The Boron concentration in our pf gates is given in the SIMS profile in fig.4. It is well above 1020cm\" throughout the gate. The difference in capacity between n+ and p' gates (fig. 3), however, indicates a lob, wide depletion in the + gate which belongs to a concentration only somewhat above 10 cm '. Clearly the process to get the Boron doping electrically active has to be optimized. The erase characteristics are shown in fig.5. Each curve has a decreasing slope followed by a second part where the flatband voltage VFB remains nearly constant. During the decreasing part the tunneling of holes is dominant (fig.2b). In the second part the electric field across the tunnel oxide has decreased and the field across the blocking oxide increased and the FN electron injection from the gate has a level as high as the hole injection from the substrate (see fig. 2c). The resulting rate of change of trapped charge in the second part of the curves is zero, so VFB is constant. At the start of the erasing the curves for p+ and n+ gates are equal. This is expected, since the electric field in the tunnel oxide is (Vgate-V~~)/Lxq, with toxq the oxide-equivalent thickness of the ONO. This field is independent of the workfunction difference between pand n-gates. Note, however, that the workfunction difference for a given VFB makes the amount of trapped charge differ for n and p gates. The minima of each erase curve vs. erase-time are again plotted in fig. 6. As examples two points with the same amount of trapped charge are marked. The one for the p+ gate is reached 5 orders of magnitude earlier. Fig. 7 shows the retention characteristics (also as size of memory window in fig. 1). The memory window at an extrapolated time of 10 years is still 3.2V. With the same retention-time criterion applied as for the conventional SONOS EEPROMs in fig.l the extrapolated retention time is 10\" years. For two different writeierase conditions the endurance characteristics are plotted in fig. 8. For the large 4V initial memory window the endurance is about 10 cycles which is comparable to other literature data /3/. For the smaller memory window the endurance comes close to lo7 cycles which is the same as the endurance of the best FLOTOX memories. Due to the excellent charge retention also smaller memory windows will be applicable. T h s can be expected to further improve the endurance. This work was supported by the Bayesische Forschungs-Stiftung. References: 1 H.E. Maes, J. Witters and G. Groeseneken, Proc. 17th European 2 F.R. Libsch and M.H. White, Solid State Electronics Vol. 33, 3 T. Bohm, A. Nakamura, H. Aosaza, M. Yamagishi and 4 Y. Hsia, IEEE Trans. Electron Devices Vol ED. 24, No. 5 , 5 E.P. Jacobs and U. Schwabe, Solid-state Electronics Vol. 24 6 P. Olivo, Z.A. Weinberg, K.J. Stein and D.S. Wen, Solid State 7 D.A. Adams, Proc. 13th Annual IEEE Nonvolatile Semicond. 8 M.L. French, C. Chen, H. Sath\"than a. M.H. White, LEEE Trans. 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引用次数: 22

Abstract

A SONOS structure with a p+ doped silicon gate instead of the commonly used n+ gate is proposed and investigated. In the erase mode the p+ gate prevents the Fowler Nordheim (FN) tunneling of electrons from the conduction band of the gate into the Si3N4. This improves either the erase speed or with a thicker tunnel oxide the data retention time by several orders of magnitude without deteriorating the other properties. Introduction SONOS memories have advantages over the FLOTOX type memories due to the superior defect density of ONO gate dielectrics compared to Si02 and due to a simpler cell structure. FLOTOX memories, however, have no problems to reach data retention times of 150 years as demanded by civil users while SONOS memories hardly reach a data retention of 10 years (see fig. 1). This is why the actual use of SONOS memories is limited to military applications needing a high radiation hardness /U. The purpose of this work is to introduce for the first time a SONOS structure with write and erase times as short as for conventional SONOS memories but with a more than 8 orders of magnitude improvement in data retention time. This is achieved with only two minor modifications of the conventional SONOS EEPROM manufacturing process. Sample Preparation Our samples were prepared by implementing an ONO storage layer (shown in the inset of fig. 3) into a standard CMOS process. The two differences to conventional SONOS memories are a 308, G e l oxide (instead of 2 0 4 and a p'-doped (with Boron) polysilicon gate instead of the standard n'-doped gate. For reference purposes the same samples with n+-gates were also prepared. For the measurements n-channel FETs as well as large area MOS diodes were used. Basic Idea The idea is explained in fig. 2: The dominant charge loss mechanism is tunneling of charge from the nitride across the tunnel oxide to the substrate / 2 / . An increase in tunnel oxide thickness from 20A to 30A will increase the data retention time by several orders of magnitude. However, inreasing the tunnel oxide thickness increases the erase time because the tunneling probability for holes from the substrate into the nitride decreases also. Increasing the field to speed up the erasing does not help because the competing process Fowler Nordheim injection of electrons from the gate prevents a total discharge of trapped negative charge (see the erase-characteristics for n' gates in fig.5). A conventional SONOS EEPROM needs, as a built-in assymetry, the tunnel oxide to be thinner than the blocking oxide in order to keep the FN current smaller than the dwect tunneling current of holes. Note that this works at low fields only. In contrast our approach makes the tunnel oxide thick and suppresses the FN current from the conduction band of the gate by instead reducing the electron density in the gate. A precondition for this concept to work is an acceptor concentration of more than 1020cm'3 in order to prevent any n-inversion or band bending due to depletion for fields as high as 10MVkm. Results and discussion The Boron concentration in our pf gates is given in the SIMS profile in fig.4. It is well above 1020cm" throughout the gate. The difference in capacity between n+ and p' gates (fig. 3), however, indicates a lob, wide depletion in the + gate which belongs to a concentration only somewhat above 10 cm '. Clearly the process to get the Boron doping electrically active has to be optimized. The erase characteristics are shown in fig.5. Each curve has a decreasing slope followed by a second part where the flatband voltage VFB remains nearly constant. During the decreasing part the tunneling of holes is dominant (fig.2b). In the second part the electric field across the tunnel oxide has decreased and the field across the blocking oxide increased and the FN electron injection from the gate has a level as high as the hole injection from the substrate (see fig. 2c). The resulting rate of change of trapped charge in the second part of the curves is zero, so VFB is constant. At the start of the erasing the curves for p+ and n+ gates are equal. This is expected, since the electric field in the tunnel oxide is (Vgate-V~~)/Lxq, with toxq the oxide-equivalent thickness of the ONO. This field is independent of the workfunction difference between pand n-gates. Note, however, that the workfunction difference for a given VFB makes the amount of trapped charge differ for n and p gates. The minima of each erase curve vs. erase-time are again plotted in fig. 6. As examples two points with the same amount of trapped charge are marked. The one for the p+ gate is reached 5 orders of magnitude earlier. Fig. 7 shows the retention characteristics (also as size of memory window in fig. 1). The memory window at an extrapolated time of 10 years is still 3.2V. With the same retention-time criterion applied as for the conventional SONOS EEPROMs in fig.l the extrapolated retention time is 10" years. For two different writeierase conditions the endurance characteristics are plotted in fig. 8. For the large 4V initial memory window the endurance is about 10 cycles which is comparable to other literature data /3/. For the smaller memory window the endurance comes close to lo7 cycles which is the same as the endurance of the best FLOTOX memories. Due to the excellent charge retention also smaller memory windows will be applicable. T h s can be expected to further improve the endurance. This work was supported by the Bayesische Forschungs-Stiftung. References: 1 H.E. Maes, J. Witters and G. Groeseneken, Proc. 17th European 2 F.R. Libsch and M.H. White, Solid State Electronics Vol. 33, 3 T. Bohm, A. Nakamura, H. Aosaza, M. Yamagishi and 4 Y. Hsia, IEEE Trans. Electron Devices Vol ED. 24, No. 5 , 5 E.P. Jacobs and U. Schwabe, Solid-state Electronics Vol. 24 6 P. Olivo, Z.A. Weinberg, K.J. Stein and D.S. Wen, Solid State 7 D.A. Adams, Proc. 13th Annual IEEE Nonvolatile Semicond. 8 M.L. French, C. Chen, H. Sath"than a. M.H. White, LEEE Trans. Yo -
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一种改进数据保留的非易失性存储器的新型SONOS结构
对于两种不同的写擦条件,持久特性绘制在图8中。对于大的4V初始存储窗口,续航时间约为10个周期,与其他文献数据相当。对于较小的内存窗口,续航时间接近lo7个周期,这与最好的FLOTOX内存的续航时间相同。由于优良的电荷保持也较小的记忆窗口将适用。这有望进一步提高续航能力。这项工作得到了Bayesische Forschungs-Stiftung的支持。参考文献:1 H.E. Maes, J. Witters和G. Groeseneken, Proc. 17 European 2 F.R. Libsch和M.H. White,固态电子学Vol. 33, 3 T. Bohm, A. Nakamura, H. Aosaza, M. Yamagishi和4 Y. Hsia, IEEE Trans。电子器件Vol. 24, No. 5, 5 E.P. Jacobs和U. Schwabe,固态电子学Vol. 24 P. Olivo, Z.A. Weinberg, K.J. Stein和D.S. Wen,固态7 d.a Adams, Proc.第13届IEEE非易失性半导体。8 M.L. French,陈正明,h.s ath"than a. M.H. White, lee Trans。哟,
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