{"title":"Salicides for 0.10 /spl mu/m gate lengths: a comparative study of one-step RTP Ti with Mo doping, Ti with pre-amorphization and Co process","authors":"Kittl, Qi-Zhong Hong, Chih-Ping Chao, Ih-Chin Chen, Ning Yu, O'Brien, Hanratty","doi":"10.1109/VLSIT.1997.623716","DOIUrl":null,"url":null,"abstract":"A study of 0.10 pm gate sheet resistance and the most relevant device characteristics comparing Ti salicide with preamorphization, Ti salicide with Molybdenum doping, and CO salicide in a fully integrated 0.18~ 1.5V CMOS technology is presented for the first time. We report the first one-step RTP Ti salicide process with MO achieving low (mean=7, max=8.1 R/sq) sheet resistance at 0.10 pn gate lengths, which results in a 34% increase in n- and PMOS DRIVE by eliminating the silicide anneal step. While low 0. lop gate sheet resistances are achieved with all these processes (a) TiSiz with MO doping of gate only and (b) COS& with high temperature RTP appear as the best suited salicides for scaled technologies with low DIODE and high DRIVE In contrast (a) DIODE increases when source and drains are also doped with MO and (b) R~D increases with As or Ge preamorphization notably as junctions are scaled down.","PeriodicalId":414778,"journal":{"name":"1997 Symposium on VLSI Technology","volume":"72 6 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1997-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"8","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"1997 Symposium on VLSI Technology","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIT.1997.623716","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 8
Abstract
A study of 0.10 pm gate sheet resistance and the most relevant device characteristics comparing Ti salicide with preamorphization, Ti salicide with Molybdenum doping, and CO salicide in a fully integrated 0.18~ 1.5V CMOS technology is presented for the first time. We report the first one-step RTP Ti salicide process with MO achieving low (mean=7, max=8.1 R/sq) sheet resistance at 0.10 pn gate lengths, which results in a 34% increase in n- and PMOS DRIVE by eliminating the silicide anneal step. While low 0. lop gate sheet resistances are achieved with all these processes (a) TiSiz with MO doping of gate only and (b) COS& with high temperature RTP appear as the best suited salicides for scaled technologies with low DIODE and high DRIVE In contrast (a) DIODE increases when source and drains are also doped with MO and (b) R~D increases with As or Ge preamorphization notably as junctions are scaled down.
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