{"title":"Interface specification and synthesis for VHDL processes","authors":"P. Gutberlet, W. Rosenstiel","doi":"10.1109/EURDAC.1993.410630","DOIUrl":null,"url":null,"abstract":"A method is presented to separate the algorithmic specification from the specification of the protocol level allowing a hierarchical design. A VHDL subset and a methodology for the specification is defined. The authors show the target architecture to merge the different levels into one synchronous data path. They present the algorithm especially dealing with the interface part of the specification. Finally, some results are given.<<ETX>>","PeriodicalId":339176,"journal":{"name":"Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference","volume":"28 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1993-09-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"10","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EURDAC.1993.410630","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 10
Abstract
A method is presented to separate the algorithmic specification from the specification of the protocol level allowing a hierarchical design. A VHDL subset and a methodology for the specification is defined. The authors show the target architecture to merge the different levels into one synchronous data path. They present the algorithm especially dealing with the interface part of the specification. Finally, some results are given.<>
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