Enhancing temporal testability and its effects on design and test generation

Abstract

Increasing controllability in the time dimension (CTD) helps test generation either by temporarily reducing the search space through freezing state variables or by simplifying the time-frame-expansion. CTD can be increased via controlling clock lines through a well defined DFT scheme, called clock line control (CLC). The design issues for controlling clock lines have been addressed. CLC can be extended to test delay faults without causing the test vector application problems as in scan design. Experimental results using ISCAS-89 circuits are shown. Better fault coverage with shorter ATG time have been achieved for the circuits with enhanced CTD