Pub Date : 1994-10-02DOI: 10.1109/TEST.1994.527939
D. Farren, A. Ambler
Unlike IC and board level test, system complexity generally limits the number of methods available to support cost-optimised system test strategy development. This paper describes a parameterised model of system behaviour during both production testing and initial field run-time. The model represents the occurrence rate of error and failure events under test and application workloads and the resulting parameters directly characterise system test effectiveness. These event rate models are fitted to actual data and incorporated into a cost function which calculates overall "cost of test" in relation to key variables. The approach is applicable to both hardware and software related events and promotes a customer view of system quality.
{"title":"System test cost modelling based on event rate analysis","authors":"D. Farren, A. Ambler","doi":"10.1109/TEST.1994.527939","DOIUrl":"https://doi.org/10.1109/TEST.1994.527939","url":null,"abstract":"Unlike IC and board level test, system complexity generally limits the number of methods available to support cost-optimised system test strategy development. This paper describes a parameterised model of system behaviour during both production testing and initial field run-time. The model represents the occurrence rate of error and failure events under test and application workloads and the resulting parameters directly characterise system test effectiveness. These event rate models are fitted to actual data and incorporated into a cost function which calculates overall \"cost of test\" in relation to key variables. The approach is applicable to both hardware and software related events and promotes a customer view of system quality.","PeriodicalId":319739,"journal":{"name":"Proceedings of 3rd International Workshop on the Economics of Design, Test and Manufacturing","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114964428","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-05-16DOI: 10.1109/ICEDTM.1994.496088
T. Ziaja, E. Swartzlander
The testing of electronic circuit boards suffers from two types of errors: Type I error occurs when a goo$ circuit board fails the test while Type II error occurs when a defectzve circuit board passes the test. Both of these errors should be considered in modeling the test process although Type II error alone has traditionally been the focus of test improvement egorts. This paper relates both error types to the defect level and to the level of good circuit boards which fail. Actual board test data as analyzed which indicates that the risk of Type I error may be as great as that for Type II error.
{"title":"Error modeling in board test","authors":"T. Ziaja, E. Swartzlander","doi":"10.1109/ICEDTM.1994.496088","DOIUrl":"https://doi.org/10.1109/ICEDTM.1994.496088","url":null,"abstract":"The testing of electronic circuit boards suffers from two types of errors: Type I error occurs when a goo$ circuit board fails the test while Type II error occurs when a defectzve circuit board passes the test. Both of these errors should be considered in modeling the test process although Type II error alone has traditionally been the focus of test improvement egorts. This paper relates both error types to the defect level and to the level of good circuit boards which fail. Actual board test data as analyzed which indicates that the risk of Type I error may be as great as that for Type II error.","PeriodicalId":319739,"journal":{"name":"Proceedings of 3rd International Workshop on the Economics of Design, Test and Manufacturing","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124920220","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-05-16DOI: 10.1109/ICEDTM.1994.496104
S. Baeg, W. A. Rogers
Increasing controllability in the time dimension (CTD) helps test generation either by temporarily reducing the search space through freezing state variables or by simplifying the time-frame-expansion. CTD can be increased via controlling clock lines through a well defined DFT scheme, called clock line control (CLC). The design issues for controlling clock lines have been addressed. CLC can be extended to test delay faults without causing the test vector application problems as in scan design. Experimental results using ISCAS-89 circuits are shown. Better fault coverage with shorter ATG time have been achieved for the circuits with enhanced CTD
{"title":"Enhancing temporal testability and its effects on design and test generation","authors":"S. Baeg, W. A. Rogers","doi":"10.1109/ICEDTM.1994.496104","DOIUrl":"https://doi.org/10.1109/ICEDTM.1994.496104","url":null,"abstract":"Increasing controllability in the time dimension (CTD) helps test\u0000generation either by temporarily reducing the search space through\u0000freezing state variables or by simplifying the time-frame-expansion. CTD\u0000can be increased via controlling clock lines through a well defined DFT\u0000scheme, called clock line control (CLC). The design issues for\u0000controlling clock lines have been addressed. CLC can be extended to test\u0000delay faults without causing the test vector application problems as in\u0000scan design. Experimental results using ISCAS-89 circuits are shown.\u0000Better fault coverage with shorter ATG time have been achieved for the\u0000circuits with enhanced CTD","PeriodicalId":319739,"journal":{"name":"Proceedings of 3rd International Workshop on the Economics of Design, Test and Manufacturing","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124890699","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-05-16DOI: 10.1109/ICEDTM.1994.496102
N. Nagi, J. Abraham
Several methods for testing the dynamic characteristics and the frequency response of analeg and mixedsignal circuits include input excitations consisting of single or multiple sine waves, pulses, pseudo/white noise or normal operating signals. These techniques differ widely in the test measurement time and the data processing time required for the frequency response characterization, as well as in their effectiveness for detecting errors. This paper will provide a comparative study of the different dynamic testing techniques in terms of the measurement and analysis times as well as test effectiveness.
{"title":"Test trade-offs for different dynamic testing techniques for analog and mixed-signal circuits","authors":"N. Nagi, J. Abraham","doi":"10.1109/ICEDTM.1994.496102","DOIUrl":"https://doi.org/10.1109/ICEDTM.1994.496102","url":null,"abstract":"Several methods for testing the dynamic characteristics and the frequency response of analeg and mixedsignal circuits include input excitations consisting of single or multiple sine waves, pulses, pseudo/white noise or normal operating signals. These techniques differ widely in the test measurement time and the data processing time required for the frequency response characterization, as well as in their effectiveness for detecting errors. This paper will provide a comparative study of the different dynamic testing techniques in terms of the measurement and analysis times as well as test effectiveness.","PeriodicalId":319739,"journal":{"name":"Proceedings of 3rd International Workshop on the Economics of Design, Test and Manufacturing","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133859654","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-05-16DOI: 10.1109/ICEDTM.1994.496091
H.B. Druckerman, M. P. Kusko, S. Pateras, P. Shephard
Test cost is becoming a major factor in today's complex chip designs. One approach to lower test cost is to have the product test, or help test, itself. There are a wide variety of Design-for-Test techniques that have been developed for this purpose. A number of these techniques are evaluated against various related cost issues.
{"title":"Cost trade-offs of various design for test techniques","authors":"H.B. Druckerman, M. P. Kusko, S. Pateras, P. Shephard","doi":"10.1109/ICEDTM.1994.496091","DOIUrl":"https://doi.org/10.1109/ICEDTM.1994.496091","url":null,"abstract":"Test cost is becoming a major factor in today's complex chip designs. One approach to lower test cost is to have the product test, or help test, itself. There are a wide variety of Design-for-Test techniques that have been developed for this purpose. A number of these techniques are evaluated against various related cost issues.","PeriodicalId":319739,"journal":{"name":"Proceedings of 3rd International Workshop on the Economics of Design, Test and Manufacturing","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122800431","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-05-16DOI: 10.1109/ICEDTM.1994.496096
S. Marallo, J. Dieffenbach
{"title":"Manufacturing cost analysis for electronic packaging","authors":"S. Marallo, J. Dieffenbach","doi":"10.1109/ICEDTM.1994.496096","DOIUrl":"https://doi.org/10.1109/ICEDTM.1994.496096","url":null,"abstract":"","PeriodicalId":319739,"journal":{"name":"Proceedings of 3rd International Workshop on the Economics of Design, Test and Manufacturing","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116571507","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-05-16DOI: 10.1109/ICEDTM.1994.496094
R.H. Williams, C. Hawkins
A method as presented which, from the customer’s point of view, connects the quality with which an arbitrary number of manufacturing tolerances are met to the manufacturer’s profit per unit. The method a+ sumes specific quadratic foms to model customer satisfaction for the three major tolerance types: nominal is best, less as better, and more as better. Theoretical and numerical examples are presented to illustrate the method for the cases of low and high quality in manuf acture.
{"title":"Economic considerations in tolerance design","authors":"R.H. Williams, C. Hawkins","doi":"10.1109/ICEDTM.1994.496094","DOIUrl":"https://doi.org/10.1109/ICEDTM.1994.496094","url":null,"abstract":"A method as presented which, from the customer’s point of view, connects the quality with which an arbitrary number of manufacturing tolerances are met to the manufacturer’s profit per unit. The method a+ sumes specific quadratic foms to model customer satisfaction for the three major tolerance types: nominal is best, less as better, and more as better. Theoretical and numerical examples are presented to illustrate the method for the cases of low and high quality in manuf acture.","PeriodicalId":319739,"journal":{"name":"Proceedings of 3rd International Workshop on the Economics of Design, Test and Manufacturing","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121736052","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-05-16DOI: 10.1109/ICEDTM.1994.496086
Y. Zorian
The increasing requirements of product quality and availability demand an effective discipline in quality assurance. The continuous expansion of the capabilities of new products, and the need to reduce their life-cycle cost and realization intervals add more stringent requirements to the above quality assurance needs. This paper discusses an approach consisting of a self-contained and reusable built-in hardware capability. In its basic form, this built-in solution performs built-in self-test, and can be extended to built-in self-diagnosis and built-in self-repair for reliability and availability purposes. Moreover, this discipline not only provides an effective quality assurance, but also helps reduce the life-cycle cost and the realization interval of a product
{"title":"Built-in quality assurance","authors":"Y. Zorian","doi":"10.1109/ICEDTM.1994.496086","DOIUrl":"https://doi.org/10.1109/ICEDTM.1994.496086","url":null,"abstract":"The increasing requirements of product quality and availability\u0000demand an effective discipline in quality assurance. The continuous\u0000expansion of the capabilities of new products, and the need to reduce\u0000their life-cycle cost and realization intervals add more stringent\u0000requirements to the above quality assurance needs. This paper discusses\u0000an approach consisting of a self-contained and reusable built-in\u0000hardware capability. In its basic form, this built-in solution performs\u0000built-in self-test, and can be extended to built-in self-diagnosis and\u0000built-in self-repair for reliability and availability purposes.\u0000Moreover, this discipline not only provides an effective quality\u0000assurance, but also helps reduce the life-cycle cost and the realization\u0000interval of a product","PeriodicalId":319739,"journal":{"name":"Proceedings of 3rd International Workshop on the Economics of Design, Test and Manufacturing","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123848379","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-05-16DOI: 10.1109/ICEDTM.1994.496084
Jiann-Liang Chen, GinKou Ma, B.-S.P. Lin
Based on the optimization theory and LaGrange multipliers concept, a novel strategy for "fair" and "economic" resource sharing in an ATM network is proposed in the paper. The main essence of proposed strategy is to confirm the minimal cost waste, that is the minimal cell loss in the ATM network, under the various negotiated Quality of Services (QoS). By doing so, consumers (senders of services) can obtain a fair share of the resources under their QoS requirements and the provider of broadband ISDN services will possess an economic operation. The tactics are realized by using the MatLab tool in a workstation.
{"title":"Economic resource sharing in ATM network","authors":"Jiann-Liang Chen, GinKou Ma, B.-S.P. Lin","doi":"10.1109/ICEDTM.1994.496084","DOIUrl":"https://doi.org/10.1109/ICEDTM.1994.496084","url":null,"abstract":"Based on the optimization theory and LaGrange multipliers concept, a novel strategy for \"fair\" and \"economic\" resource sharing in an ATM network is proposed in the paper. The main essence of proposed strategy is to confirm the minimal cost waste, that is the minimal cell loss in the ATM network, under the various negotiated Quality of Services (QoS). By doing so, consumers (senders of services) can obtain a fair share of the resources under their QoS requirements and the provider of broadband ISDN services will possess an economic operation. The tactics are realized by using the MatLab tool in a workstation.","PeriodicalId":319739,"journal":{"name":"Proceedings of 3rd International Workshop on the Economics of Design, Test and Manufacturing","volume":"164 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124600189","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-05-16DOI: 10.1109/ICEDTM.1994.496101
J. T. Healy
Next generation ICs for multimedia, mobile communications, will demand efficient, integrated manufacturing, testing processes and equipment. New IC applications serving mobile communications, multimedia and personal digital products will by the middle of this decade create significant changes in semiconductor production and test. Smaller geometries and larger wafers create the requirements for highly stable manufacturing conditions, a contamination-free environment, and very precise equipment. New fabrication construction costs for these ICs will exceed $1 billion per facility, forcing IC producers to look at alternatives from cluster manufacturing to new packaging efficiencies. In addition, functional testing will need to move as far forward in the production process as possible, in order to remove bad product early and cut costs. Testing will be integrated as seamlessly as possible into the manufacturing process. This paper explores manufacturing and test issues pertinent to the production of the new generation of ICs, focusing on the trends in new production and test equipment that is already beginning to show up in advanced facilities and will proliferate by the year 2000
{"title":"The need for highly integrated manufacturing test equipment","authors":"J. T. Healy","doi":"10.1109/ICEDTM.1994.496101","DOIUrl":"https://doi.org/10.1109/ICEDTM.1994.496101","url":null,"abstract":"Next generation ICs for multimedia, mobile communications, will\u0000demand efficient, integrated manufacturing, testing processes and\u0000equipment. New IC applications serving mobile communications, multimedia\u0000and personal digital products will by the middle of this decade create\u0000significant changes in semiconductor production and test. Smaller\u0000geometries and larger wafers create the requirements for highly stable\u0000manufacturing conditions, a contamination-free environment, and very\u0000precise equipment. New fabrication construction costs for these ICs will\u0000exceed $1 billion per facility, forcing IC producers to look at\u0000alternatives from cluster manufacturing to new packaging efficiencies.\u0000In addition, functional testing will need to move as far forward in the\u0000production process as possible, in order to remove bad product early and\u0000cut costs. Testing will be integrated as seamlessly as possible into the\u0000manufacturing process. This paper explores manufacturing and test issues\u0000pertinent to the production of the new generation of ICs, focusing on\u0000the trends in new production and test equipment that is already\u0000beginning to show up in advanced facilities and will proliferate by the\u0000year 2000","PeriodicalId":319739,"journal":{"name":"Proceedings of 3rd International Workshop on the Economics of Design, Test and Manufacturing","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115936620","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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