Mechanical Stress Induced MOSFET Punch-through And Process Optimization For Deep Submicron TEOS-O/sub 3/ Filled STI Device

Abstract

Introduction Shallow trench isolation (STI) is the key technology for deep submicron devices and begins to be used practically for advanced logic and memory LSIs. With down-scaling of device dimensions, the aspect ratio of trench increases and trench filling becomes severe even in STI structures. Therefore, choice of filling material for high aspect ratio trench is one of the important issues for deep submicron STI devices. Although the TEOS-Q film shows good refilling characteristics, it requires high temperature annealing in order to minimize HF etch-rate and this high temperature process results in large volume change with high mechanical stress [I] . However, the impact of this stress on device functionality and process optimization have not been investigated. In this paper, mechanical stress induced defect generation accompanying the MOSFET punch-through in TEOS-Q filled STI structure is reported for the first time. This defect is located only in channel region beneath the gate oxide and causes enhanced diffusion of sourceidrain impurity. The residual mechanical stress of filling material and the gate electrode cause this phenomenon. Suppression of the defect generation by optimizing high temperature annealing process is also described and is verified by SRAM test vehicle. Mechanical Stress-induced MOSFET Punch-through The fabrication process of MOSFET with STI structure was based on 0.35pm technology [2]. The trench depth was 0.7pm to achieve 0.4pm n+ip+ spacing. The channel width of each transistor used in memory cell was 0.35pm and the isolation width was 0.4pm. The TEOS-Q film was used as a filling material to fill such high aspect ratio trenches. After CMP planarization, high temperature (>lOOOT) annealing was carried out to minimize HF etch-rate similar to thermal oxide. The gate electrode was consist of poly-Si(200nm)~WSi(100nm)/SiN(200nm) stacked structure and lOOnm thick SiN sidewall was applied. In order to verify the manufacturability of this process, thousands of SRAM test vehicles (256kbit) were fabricated. As a result, it was found that some SRAM chips suffer from specific functional failure with large stand-by current more than 10pAifail-bit. The leakage current level was higher four order of magnitude than that of junction leakage current of total active region. Moreover, the leakage current had negative temperature dependence and was same as the nMOS inverter's. These results suggest that some access transistor in cell array did not cut-off with very small probability. In fact, it was verified that an access transistor in the fail chip had large sourceidrain punch-through current. Therefore, it was concluded that the leakage current flew from bit-line to Vss-line through nMOS inverter consisted of access transistor and latch nMOS as shown in Fig.1. The I-V characteristic of access transistor in cell array which accompanies source/drain punchthrough characteristic is also shown in Fig.2. It should be noted that this current is not a gate leakage current nor a junction leakage current of sourceidrain region. A n a l y s i s The origin of the punch-through phenomenon was studied. Figure 3 (a) shows SEM photograph of 0.35pm 6T SRAM cell after Wright etching which shows sourceidrain punch-through characteristics. As shown in the photograph, needlelike extended sourceidrain region was observed. It is considered that this enhanced sourceidrain impurity diffusion is caused by the defect along the channel, since the cross sectional TEM photograph reveals that crystal defects are formed in this channel region as shown in Fig.S(b). It should be noted that this defect appears beneath of the gate oxide and clearly different from the ionimplantation-induced defect at sourceidrain region. Moreover, this defect was observed only in access transistors and not observed latch transistors of memory cell. In order to analyze this phenomenon, stress simulation was carried out by ABAQUS. Figure 4 shows simulated maximum Mises stress of active region of 6T cell in case that TEOS-03 annealing temperature was 1000°C. The channel region with concave comer shows maximum Mises stress more than 300MPa and corresponds to the region where channel defect appears as shown in Fig.3(a). Additional factor of this defect generation is the material stress of the gate electrode. There was a report about W polycide gate stress which causes dislocation in LOCOS structure [3]. As shown in the Fig.3(a), this defect was observed only access transistor region, though both access and latch transistor have concave corner. The difference between these transistors are the total gate electrode length. In the 6T cell structure, the gate electrode length of latch by nMOS and PMOS is about 3 ~ m as shown in the cell layout of Fig.3. On the other hand, the gate electrode of access transistor (word line) was connected with more than 50 cells and its total length exceeds 100pm. From above results, it is concluded that mechanical stress by filling material and additional stress by the gate electrode material cause this defect generation in channel region. Process Optimization Process integration for avoiding the mechanical stress induced sourceidrain punch-through was also studied. The relaxation of residual stress is the fundamental solution of this problem. Since process temperature after STI formation is 8O0-85O0C, i t is important to reduce mechanical stress around this temperature. In order to minimize residual stress of the filling materials, high temperature annealing after trench filling step was investigated. Figure 5 shows temperature dependence of TEOS-03 film stress as a parameter of annealing temperature. By 1200°C annealing, TEOS0 3 films stress at 850°C decreased to =OMPa while 1000°C annealed sample shows more than 1GPa. Annealing temperature dependence of defect density is also shown in Fig.6. As shown in the figure, 1 2 0 0 ° C annealed sample shows defect free characteristics. The impact of 1200°C annealing on suppressing defect-induced MOSFET punch-through is shown in Fig.7. It was confirmed that TEOS-03 filled STI can be applied to 0.35pm 6T cell without degrading device yield by introducing optimized high temperature annealing. Moreover, simulated mechanical stress indicates that 10% size reduction in channel width increases the mechanical stress about 5% as shown in Fig.8. This result means that down-scaling of STI device dimensions in future LSIs will require careful procesdmaterial design as mentioned above for achieving lower mechanical stress and higher manufacturability. Conclusion Sourceidrain punch-through due to channel defect in TEoS-03 filled STI structure was found for the first time. This defect generation was caused by residual stress of filling material and assisted by the gate electrode material stress. Optimized high temperature annealing achieved defect free characteristics and enabled TEOS-03 as a filling material of STI structure without degrading device yield. Process integration for future STI devices should take account of this phenomenon carefully from a manufactuability point of view. References [ I 1 S . Nag et al., IEDM Tech. Dig., p841, 1996 [21 K. Ishimam et al., Symp. on VLSI Tech., p97, 1994 [31 S . Ikeda et al., IEDM Tech. Dig., p77, 1996