Y. Liu, T. Kamei, T. Matsukawa, K. Endo, S. O'Uchi, J. Tsukada, H. Yamauchi, Y. Ishikawa, T. Hayashida, K. Sakamoto, A. Ogura, M. Masahara
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引用次数: 3
Abstract
It was experimentally confirmed that smaller Vt variations, better SCE immunity and a large memory window are obtained in the TG type SOI-FinFET flash memories than the DG type ones. The highly suppressed over erase was confirmed in the split-gate FinFET flash memories. Introducing a thin thermal oxide layer on the FG is useful to improve the IPD layer quality.
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