A. Demosthenous, R. Akbari-Dilmaghani, S. Smedley, John T. Taylor
{"title":"Enhanced modular CMOS current-mode winner-take-all network","authors":"A. Demosthenous, R. Akbari-Dilmaghani, S. Smedley, John T. Taylor","doi":"10.1109/ICECS.1996.582856","DOIUrl":null,"url":null,"abstract":"A CMOS modular high-speed current-mode 2-input Winner-Take-All (2-WTA) circuit for use in VLSI tree-structure WTA networks is described. The classification speed of the design is not input pattern dependent, but is a function of the value of the largest current input only. The complexity of the proposed WTA is O(M), but unlike other architectures, mismatch errors accumulate at a rate proportional to log/sub 2/M. Since for large M this is a slowly increasing function of M, the proposed arrangement is well suited to large WTA systems. Simulations show that the proposed circuit can resolve input currents differing by less than 1/spl mu/A with only a small loss of operating speed. Detailed simulations and measured results of a single 2-WTA cell and of a complete 8-input tree WTA are presented.","PeriodicalId":402369,"journal":{"name":"Proceedings of Third International Conference on Electronics, Circuits, and Systems","volume":"6 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1996-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of Third International Conference on Electronics, Circuits, and Systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICECS.1996.582856","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 5
Abstract
A CMOS modular high-speed current-mode 2-input Winner-Take-All (2-WTA) circuit for use in VLSI tree-structure WTA networks is described. The classification speed of the design is not input pattern dependent, but is a function of the value of the largest current input only. The complexity of the proposed WTA is O(M), but unlike other architectures, mismatch errors accumulate at a rate proportional to log/sub 2/M. Since for large M this is a slowly increasing function of M, the proposed arrangement is well suited to large WTA systems. Simulations show that the proposed circuit can resolve input currents differing by less than 1/spl mu/A with only a small loss of operating speed. Detailed simulations and measured results of a single 2-WTA cell and of a complete 8-input tree WTA are presented.