Enhanced modular CMOS current-mode winner-take-all network

Abstract

A CMOS modular high-speed current-mode 2-input Winner-Take-All (2-WTA) circuit for use in VLSI tree-structure WTA networks is described. The classification speed of the design is not input pattern dependent, but is a function of the value of the largest current input only. The complexity of the proposed WTA is O(M), but unlike other architectures, mismatch errors accumulate at a rate proportional to log/sub 2/M. Since for large M this is a slowly increasing function of M, the proposed arrangement is well suited to large WTA systems. Simulations show that the proposed circuit can resolve input currents differing by less than 1/spl mu/A with only a small loss of operating speed. Detailed simulations and measured results of a single 2-WTA cell and of a complete 8-input tree WTA are presented.