Enhanced modular CMOS current-mode winner-take-all network

A. Demosthenous, R. Akbari-Dilmaghani, S. Smedley, John T. Taylor
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引用次数: 5

Abstract

A CMOS modular high-speed current-mode 2-input Winner-Take-All (2-WTA) circuit for use in VLSI tree-structure WTA networks is described. The classification speed of the design is not input pattern dependent, but is a function of the value of the largest current input only. The complexity of the proposed WTA is O(M), but unlike other architectures, mismatch errors accumulate at a rate proportional to log/sub 2/M. Since for large M this is a slowly increasing function of M, the proposed arrangement is well suited to large WTA systems. Simulations show that the proposed circuit can resolve input currents differing by less than 1/spl mu/A with only a small loss of operating speed. Detailed simulations and measured results of a single 2-WTA cell and of a complete 8-input tree WTA are presented.
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增强型模块化CMOS电流模式赢家通吃网络
描述了一种用于VLSI树状结构WTA网络的CMOS模块化高速电流模式2输入赢者通吃(2-WTA)电路。设计的分类速度不依赖于输入模式,而仅是最大电流输入值的函数。所提出的WTA的复杂性为0 (M),但与其他体系结构不同的是,不匹配错误以与log/sub 2/M成比例的速率累积。由于对于较大的M,这是M的缓慢增长函数,因此所提出的安排非常适合于大型WTA系统。仿真结果表明,该电路可以分辨输入电流差小于1/spl mu/A的情况下,运行速度损失很小。给出了单个2-WTA单元和完整的8输入树WTA的详细模拟和测量结果。
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