{"title":"Examination of residual stress measurement in electronic packages using phase-shifted sampling moiré method and X-ray images","authors":"M. Koganemaru, M. Uchino, A. Ikeda, T. Asano","doi":"10.1109/ESTC.2014.6962827","DOIUrl":null,"url":null,"abstract":"This paper examines a novel approach to measure residual stresses in an electronic package. The presented method applies a phase-shifted sampling moiré method to X-ray images of the test chip (Si) in the electronic package. In this study, the test chip including an Au bump grid are made by general semiconductor processes for forming Au bumps on Si chip, and X-ray images of the test chip are taken before and after packaging (resin-molding). Then the phase difference of the sampling moiré fringe patterns before and after packaging can be obtained from the X-ray images of the test chip before and after packaging. The phase difference corresponds to the deformation of the test chip. The results of this examination indicate that the presented method is possible to be used for measuring residual stresses in electronic packages.","PeriodicalId":299981,"journal":{"name":"Proceedings of the 5th Electronics System-integration Technology Conference (ESTC)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2014-11-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the 5th Electronics System-integration Technology Conference (ESTC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ESTC.2014.6962827","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
This paper examines a novel approach to measure residual stresses in an electronic package. The presented method applies a phase-shifted sampling moiré method to X-ray images of the test chip (Si) in the electronic package. In this study, the test chip including an Au bump grid are made by general semiconductor processes for forming Au bumps on Si chip, and X-ray images of the test chip are taken before and after packaging (resin-molding). Then the phase difference of the sampling moiré fringe patterns before and after packaging can be obtained from the X-ray images of the test chip before and after packaging. The phase difference corresponds to the deformation of the test chip. The results of this examination indicate that the presented method is possible to be used for measuring residual stresses in electronic packages.