Test generation based on synthesizable VHDL descriptions

Abstract

Modern complex ASIC chips contain numerous registers, counters, and control units (state sequencers), making it extremely difficult for gate level sequential circuit test generation techniques to generate good test vectors in a reasonable time. The authors present a methodology which uses functional information extracted from a VHDL behavior model to drive the test generation process. As opposed to various behavior test generation systems proposed recently which use behavior fault models, the proposed system uses the standard stuck-at fault model of logic elements. Thus, the fault coverage figures reported by the system can readily be verified by other commercially available fault simulators.<>