A VLSI structural optimization method and workflow based on synthesis frequency inflexion

Abstract

A synthesis frequency inflexion phenomenon of VLSI synthesis process is discussed, and then a VLSI structural optimization method with its workflow based on the analysis of synthesis frequency infrexion and register insertion is proposed. Registers are usually used for sequential synchronization and increasing maximum operating frequency, but in this issue, they are utilized to avoid excessively high combinational logic expenditure. In the H.264 macroblock-level SAD tree case, 50.6% improvement in speed is achieved at the expense of 2.9% increment in area. This method contains no complex algorithm, but exhibits good operability and generality. It is very suitable and useful for complicated VLSI structural design and/or their critical path optimization.