Specification Driven Design of Phase Locked Loops

Abstract

The factors that impact the topology and the performance specifications for a Phase locked loop (PLL) is presented. Correct specification of the PLL is critical for optimizing the performance and power of the system. PLL specifications for different systems have been derived and the architectural tradeoffs have been discussed. Three PLL design examples have been presented for WLAN base-bandPLL application, DVB-H receiver base-band PLL application and a high speed (MIPI) transmitter application.