Why would an ASIC foundry accept anything less than full scan?

Abstract

A key force behind IBM's growth in the application-specific integrated circuit (ASIC) market is the ability to sign off on multi-million-gate designs without requiring test vectors, presenting a savings in both time and money to customers. Once a customer ensures (via formal verification and/or functional simulation) that the design functions as required, static tinting analysis (STA) ensures that the design achieves the required performance targets. Extensive model-to-hardware correlation assures correctness of the timing analysis models, enabling IBM to assure that the design can be manufactured to the required performance targets. Through a combination of full-scan and boundary-scan design-for-test (DFT) structures, the IBM ASIC methodology ensures that automatically generated test patterns will run correctly on test equipment; typically achieving 99+% stuck-fault coverage. In the case of a repeatable manufacturing defect, full-scan-based diagnostic software isolates the problem without customer involvement.