High-density DRAM package simulation

Abstract

This paper presents the results of a two-part study to investigate the package and board-level thermo-mechanical reliability of a 2-COB/4-COB high-density multichip package for highperformance server applications. The first part of this paper presents package-level simulation performed on 2-COB/4-COB packages showed that the packages experienced very high localized stress at the active surface edge of the bottom die. This was due to a localized stiffness and thermal coefficient of expansion mismatch between the silicon die, epoxy, and mold compound. In particular, the mismatch occurred in the resin-rich region and the area of incomplete epoxy coverage. Simulation demonstrated that the model with silicon spacer die stacking technology significantly reduced stress, and was adopted as a solution to improve the package reliability performance. The second part of this paper presents results for board-level simulation conducted to understand the effect of die stacking methods (silicon spacer, epoxy, and film-over-wire) on solder joint reliability. Results indicate that conversion to the silicon spacer stack method solves package-level reliability issues at the expense of board-level solder joint reliability (SJR). This can jeopardize the ability of the product to meet customer with more stringent requirements. Therefore, a fine balance between packaging and board-level reliability must be achieved. As a follow-up to this study, a work was initiated to improve boardlevel SJR for multiple large die stack packages in order to improve the performance margin.