{"title":"Copper Integration In Self Aligned Dual Damascene Architecture","authors":"Morand, Lermé, Palleau, Torres, Vinet, Demolliens, Ulmer, Gobil, Fayolle, Romagna, Le Bihan","doi":"10.1109/VLSIT.1997.623680","DOIUrl":null,"url":null,"abstract":"In this paper, we will demonstrate the compatibility of copper metallization in a Self Aligned Dual Damascene architecture with 0.18pm CMOS technology requirements. This Cu metallization has also been used, for the first time, as the fifth level of metal of a 2cm2 0.35pm microprocessor for integrability demonstration on 200\" wafers.","PeriodicalId":414778,"journal":{"name":"1997 Symposium on VLSI Technology","volume":"27 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1997-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"10","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"1997 Symposium on VLSI Technology","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIT.1997.623680","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 10
Abstract
In this paper, we will demonstrate the compatibility of copper metallization in a Self Aligned Dual Damascene architecture with 0.18pm CMOS technology requirements. This Cu metallization has also been used, for the first time, as the fifth level of metal of a 2cm2 0.35pm microprocessor for integrability demonstration on 200" wafers.
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