A ROM based low-power multiplier

Abstract

We present a ROM based 16times16 multiplier for low power applications. The design uses sixteen 4times4 ROM based multiplier blocks followed by carry save adders and a final carry select adder (all ROM based) to obtain the 32 bit output. All ROM blocks are implemented using single transistor ROM cells and eliminating identical rows and columns for optimizing the power and performance. Measurement results in 0.18 mum CMOS process show a 40% reduction in power over the conventional carry save array multiplier when operated at its maximum frequency. The ROM based design also provides 44% less delay than the array multiplier with a minimal increase (7.7%) in power. This demonstrates the low-power operation of the ROM based multiplier also at higher frequencies.