J. Carrere, F. Larman, E. van der Vegt, M. Bocat, N. Auriac, N. Cherault, M. Charleux, K. Rochereau, M. Hopstaken, R. Pantel, D. Boter, D. Dormans
{"title":"Embedded FLASH memory thermal budget impact on core CMOS 90nm devices","authors":"J. Carrere, F. Larman, E. van der Vegt, M. Bocat, N. Auriac, N. Cherault, M. Charleux, K. Rochereau, M. Hopstaken, R. Pantel, D. Boter, D. Dormans","doi":"10.1109/ESSDERC.2007.4430928","DOIUrl":null,"url":null,"abstract":"In an embedded FLASH 90 nm technology, core devices behavior is modified by the thermal budget needed to process the specific FLASH dielectrics. When these steps are performed after the logic poly deposition, we observe two main kinds of changes: first the substrate doping is modified due to diffusion and segregation effects. Then, the poly morphology changes, this leads to larger poly grain size and gate doping change. To limit these effects and maintain the full compatibility with CMOS logic, thermal budget limitations are finally presented.","PeriodicalId":103959,"journal":{"name":"ESSDERC 2007 - 37th European Solid State Device Research Conference","volume":"19 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"ESSDERC 2007 - 37th European Solid State Device Research Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ESSDERC.2007.4430928","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
Abstract
In an embedded FLASH 90 nm technology, core devices behavior is modified by the thermal budget needed to process the specific FLASH dielectrics. When these steps are performed after the logic poly deposition, we observe two main kinds of changes: first the substrate doping is modified due to diffusion and segregation effects. Then, the poly morphology changes, this leads to larger poly grain size and gate doping change. To limit these effects and maintain the full compatibility with CMOS logic, thermal budget limitations are finally presented.