Hong Shi, S. Tan, G. Refai-Ahmed, S. Ramalingam, Jae-Gyung Ahn
{"title":"High power FPGA package design to maximize current-carrying capability","authors":"Hong Shi, S. Tan, G. Refai-Ahmed, S. Ramalingam, Jae-Gyung Ahn","doi":"10.1109/EDAPS.2016.7893121","DOIUrl":null,"url":null,"abstract":"The recent market demand to high power 16nm FPGA has challenged package design to an unprecedented level. Specifically, logic tense applications require significantly greater dynamic current than previous generations. This paper describes recent advancements in high power FPGA package design for current-carrying capability. Firstly, new design methodologies are introduced that can link physical design for optimal current distribution directly to failure rate as a result of electro-migration (EM) in stated lifetime. Secondly, a specific design case is analyzed with the new method to show how BGA pin pattern can impact maximal current carrying capability.","PeriodicalId":191549,"journal":{"name":"2016 IEEE Electrical Design of Advanced Packaging and Systems (EDAPS)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 IEEE Electrical Design of Advanced Packaging and Systems (EDAPS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EDAPS.2016.7893121","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
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Abstract
The recent market demand to high power 16nm FPGA has challenged package design to an unprecedented level. Specifically, logic tense applications require significantly greater dynamic current than previous generations. This paper describes recent advancements in high power FPGA package design for current-carrying capability. Firstly, new design methodologies are introduced that can link physical design for optimal current distribution directly to failure rate as a result of electro-migration (EM) in stated lifetime. Secondly, a specific design case is analyzed with the new method to show how BGA pin pattern can impact maximal current carrying capability.
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