Pub Date : 2016-12-01DOI: 10.1109/EDAPS.2016.7874442
H. Braunisch, A. Elsherbini
Based on the recognition that propagating near-end crosstalk is the primary source of crosstalk noise in short unterminated channels we describe and demonstrate an approach to improve the signal integrity on such channels significantly. The basic physics and Norton formulation of crosstalk reduction by matrix matching are described. We then show large potential gains for two on-package interconnect application examples. A nominal strip line configuration based on standard package design rules and including realistic modeling assumptions yields 50.4% reduced channel power at iso-performance. The same design can be converted to microstrip without degrading eye height and channel power.
{"title":"Crosstalk reduction by matrix matching","authors":"H. Braunisch, A. Elsherbini","doi":"10.1109/EDAPS.2016.7874442","DOIUrl":"https://doi.org/10.1109/EDAPS.2016.7874442","url":null,"abstract":"Based on the recognition that propagating near-end crosstalk is the primary source of crosstalk noise in short unterminated channels we describe and demonstrate an approach to improve the signal integrity on such channels significantly. The basic physics and Norton formulation of crosstalk reduction by matrix matching are described. We then show large potential gains for two on-package interconnect application examples. A nominal strip line configuration based on standard package design rules and including realistic modeling assumptions yields 50.4% reduced channel power at iso-performance. The same design can be converted to microstrip without degrading eye height and channel power.","PeriodicalId":191549,"journal":{"name":"2016 IEEE Electrical Design of Advanced Packaging and Systems (EDAPS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130182845","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-12-01DOI: 10.1109/EDAPS.2016.7874430
Y. Shlepnev
Design and compliance analysis of PCB and packaging interconnects for 10–50 Gbps and higher data rates should begin with the identification of broadband dielectric and conductor roughness models. Such models are not available from manufacturers and the model identification is the most important element of successful interconnect design. Broadband model identification with generalized modal S-parameters (GMS-parameters) is outlined and compared with the standardized Short Pulse Propagation (SPP) technique. Practical examples of successful dielectric and conductor roughness model identification up to 50 GHz are also provided.
{"title":"Broadband material model identification with GMS-parameters","authors":"Y. Shlepnev","doi":"10.1109/EDAPS.2016.7874430","DOIUrl":"https://doi.org/10.1109/EDAPS.2016.7874430","url":null,"abstract":"Design and compliance analysis of PCB and packaging interconnects for 10–50 Gbps and higher data rates should begin with the identification of broadband dielectric and conductor roughness models. Such models are not available from manufacturers and the model identification is the most important element of successful interconnect design. Broadband model identification with generalized modal S-parameters (GMS-parameters) is outlined and compared with the standardized Short Pulse Propagation (SPP) technique. Practical examples of successful dielectric and conductor roughness model identification up to 50 GHz are also provided.","PeriodicalId":191549,"journal":{"name":"2016 IEEE Electrical Design of Advanced Packaging and Systems (EDAPS)","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115602366","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-12-01DOI: 10.1109/EDAPS.2016.7874422
David C. Zhang, M. Swaminathan, D. Keezer
Transmission lines carrying high speed I/O signals can couple significant amount of electromagnetic energy to power distribution network (PDN) which can then adversely affect signal and power integrity of the entire electrical system. Similarly the reverse is also true. In this paper we present three printed circuit board designs with different power distribution topologies and show through measurement that a previously proposed PDN design based on Power Transmission Line (PTL) concept is less susceptible to coupling from signal lines.
{"title":"Reduction of PDN induced coupling into signal lines using PTL power distribution","authors":"David C. Zhang, M. Swaminathan, D. Keezer","doi":"10.1109/EDAPS.2016.7874422","DOIUrl":"https://doi.org/10.1109/EDAPS.2016.7874422","url":null,"abstract":"Transmission lines carrying high speed I/O signals can couple significant amount of electromagnetic energy to power distribution network (PDN) which can then adversely affect signal and power integrity of the entire electrical system. Similarly the reverse is also true. In this paper we present three printed circuit board designs with different power distribution topologies and show through measurement that a previously proposed PDN design based on Power Transmission Line (PTL) concept is less susceptible to coupling from signal lines.","PeriodicalId":191549,"journal":{"name":"2016 IEEE Electrical Design of Advanced Packaging and Systems (EDAPS)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121961972","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-12-01DOI: 10.1109/EDAPS.2016.7874438
Maryam Hajimiri, J. Schutt-Ainé
This paper presents an approach for the transient simulation of circuits through the latency insertion model using advanced models for MOS transistors. By taking into account the dynamic charge storage effects in short-channel devices a more accurate simulation of high-speed digital and analog circuits via the latency insertion method can be performed. The approach makes use of the SPICE LEVEL 3 transistor model for MOSFETs. In addition the use of the latency insertion method allows better convergence and higher computational speed for the simulation. Several computer simulations are performed to validate the method. Results show improvement in accuracy by using the high-level models.
{"title":"MOS models for LIM transient simulations","authors":"Maryam Hajimiri, J. Schutt-Ainé","doi":"10.1109/EDAPS.2016.7874438","DOIUrl":"https://doi.org/10.1109/EDAPS.2016.7874438","url":null,"abstract":"This paper presents an approach for the transient simulation of circuits through the latency insertion model using advanced models for MOS transistors. By taking into account the dynamic charge storage effects in short-channel devices a more accurate simulation of high-speed digital and analog circuits via the latency insertion method can be performed. The approach makes use of the SPICE LEVEL 3 transistor model for MOSFETs. In addition the use of the latency insertion method allows better convergence and higher computational speed for the simulation. Several computer simulations are performed to validate the method. Results show improvement in accuracy by using the high-level models.","PeriodicalId":191549,"journal":{"name":"2016 IEEE Electrical Design of Advanced Packaging and Systems (EDAPS)","volume":"135 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125233799","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-12-01DOI: 10.1109/EDAPS.2016.7874443
H. Wakita, M. Nagatani, H. Nosaka
This paper presents a small quad-channel driver module for optical modulators in digital coherent systems. To decrease the size of the module, we designed a compact quad-channel package. The size of the package is 14 × 8 × 2.8 mm3. The bandwidth of the driver module is 36 GHz with maximum differential gain of 15 dB. Waveforms with clear eye-openings at symbol rates of 32 and 50 Gbaud were observed. To the best of our knowledge, this is the most compact quad-channel driver module in 50-Gbaud class.
{"title":"36-GHz-bandwidth quad-channel driver module using compact QFN package for optical coherent systems","authors":"H. Wakita, M. Nagatani, H. Nosaka","doi":"10.1109/EDAPS.2016.7874443","DOIUrl":"https://doi.org/10.1109/EDAPS.2016.7874443","url":null,"abstract":"This paper presents a small quad-channel driver module for optical modulators in digital coherent systems. To decrease the size of the module, we designed a compact quad-channel package. The size of the package is 14 × 8 × 2.8 mm3. The bandwidth of the driver module is 36 GHz with maximum differential gain of 15 dB. Waveforms with clear eye-openings at symbol rates of 32 and 50 Gbaud were observed. To the best of our knowledge, this is the most compact quad-channel driver module in 50-Gbaud class.","PeriodicalId":191549,"journal":{"name":"2016 IEEE Electrical Design of Advanced Packaging and Systems (EDAPS)","volume":"16 17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117154289","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-12-01DOI: 10.1109/EDAPS.2016.7874440
V. Dmitriev-Zdorov
Do statistical methods developed for NRZ signals work for PAM-4 modulation? Not entirely. We show that some basic principles (e.g., edge-based analysis, conversion of jitter PDF into vertical noise) remain valid, but the solution flow should be modified. Modifications include: the number of PMF accumulators, their initialization and input-output connections, weight factors, transition probabilities, and their relationships to the high-order correlation coefficients.
{"title":"Accurate statistical analysis of high-speed links with PAM-4 modulation considering transmit jitter, data-dependent transitions, and correlated input patterns","authors":"V. Dmitriev-Zdorov","doi":"10.1109/EDAPS.2016.7874440","DOIUrl":"https://doi.org/10.1109/EDAPS.2016.7874440","url":null,"abstract":"Do statistical methods developed for NRZ signals work for PAM-4 modulation? Not entirely. We show that some basic principles (e.g., edge-based analysis, conversion of jitter PDF into vertical noise) remain valid, but the solution flow should be modified. Modifications include: the number of PMF accumulators, their initialization and input-output connections, weight factors, transition probabilities, and their relationships to the high-order correlation coefficients.","PeriodicalId":191549,"journal":{"name":"2016 IEEE Electrical Design of Advanced Packaging and Systems (EDAPS)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124867653","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-12-01DOI: 10.1109/EDAPS.2016.7874405
C. Luo, Giacomo Bianconi, Swagato Chakraborty
The paper presents an efficient and accurate methodology for evaluating near singular Green's function integrals for 3D boundary element-based full-wave analysis of interconnect structures in IC packages and printed circuit boards using quadrilateral basis function.
{"title":"Evaluation of near-singular integrals for quadrilateral basis in integral equation solver","authors":"C. Luo, Giacomo Bianconi, Swagato Chakraborty","doi":"10.1109/EDAPS.2016.7874405","DOIUrl":"https://doi.org/10.1109/EDAPS.2016.7874405","url":null,"abstract":"The paper presents an efficient and accurate methodology for evaluating near singular Green's function integrals for 3D boundary element-based full-wave analysis of interconnect structures in IC packages and printed circuit boards using quadrilateral basis function.","PeriodicalId":191549,"journal":{"name":"2016 IEEE Electrical Design of Advanced Packaging and Systems (EDAPS)","volume":"82 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121707823","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-12-01DOI: 10.1109/EDAPS.2016.7874409
Nikita Ambasanal, Bhyrav Mutnuryz, Dipanjan Gopel
IRIS is a consolidated platform to analyse bulk S-Parameter data, perform operations like termination/renormalization of port impedances, conversion from single-ended to mixed mode, evaluate complex equations in S-Parameters, plug-in, View and record Violation of envelopes as defined by SATA, SAS, PCIe & USB spec sheets. It also implements a novel machine-learning based methodology [1] to efficiently bridge Frequency Domain (FD) and Time Domain (TD) by predicting Eye-Height (EH) and Eye-Widths (EW) from S-Parameters.
{"title":"Intelligent rapid investigation of S-Parameters (IRIS): Frequency & time domain channel analyzer","authors":"Nikita Ambasanal, Bhyrav Mutnuryz, Dipanjan Gopel","doi":"10.1109/EDAPS.2016.7874409","DOIUrl":"https://doi.org/10.1109/EDAPS.2016.7874409","url":null,"abstract":"IRIS is a consolidated platform to analyse bulk S-Parameter data, perform operations like termination/renormalization of port impedances, conversion from single-ended to mixed mode, evaluate complex equations in S-Parameters, plug-in, View and record Violation of envelopes as defined by SATA, SAS, PCIe & USB spec sheets. It also implements a novel machine-learning based methodology [1] to efficiently bridge Frequency Domain (FD) and Time Domain (TD) by predicting Eye-Height (EH) and Eye-Widths (EW) from S-Parameters.","PeriodicalId":191549,"journal":{"name":"2016 IEEE Electrical Design of Advanced Packaging and Systems (EDAPS)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131024317","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-12-01DOI: 10.1109/EDAPS.2016.7874436
X. Deng, B. Nouri, M. Nakhla
A novel projection framework is presented for constructing stable reduced macromodels for stable active linear circuits. Stability preservation is a necessary property for time-domain simulation. The proposed method is based on an efficient algorithm for computing the projection matrices. The validity of the proposed method is demonstrated using numerical example.
{"title":"Stability preserving algorithm for model order reduction of active networks","authors":"X. Deng, B. Nouri, M. Nakhla","doi":"10.1109/EDAPS.2016.7874436","DOIUrl":"https://doi.org/10.1109/EDAPS.2016.7874436","url":null,"abstract":"A novel projection framework is presented for constructing stable reduced macromodels for stable active linear circuits. Stability preservation is a necessary property for time-domain simulation. The proposed method is based on an efficient algorithm for computing the projection matrices. The validity of the proposed method is demonstrated using numerical example.","PeriodicalId":191549,"journal":{"name":"2016 IEEE Electrical Design of Advanced Packaging and Systems (EDAPS)","volume":"2673 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123619887","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-12-01DOI: 10.1109/EDAPS.2016.7874408
N. Dikhaminjia, J. He, E. Hernandez, M. Tsiklauri, J. Drewniak, A. Chada, M. Zvonkin, B. Mutnury
The paper discusses challenges of high-speed serial links using multi-level signaling and gives comparison of the performance of the various channels with different lossy materials and equalization options. Advantages and problems of multi-level signaling are shown based on the test results.
{"title":"High-speed serial link challenges using multi-level signaling","authors":"N. Dikhaminjia, J. He, E. Hernandez, M. Tsiklauri, J. Drewniak, A. Chada, M. Zvonkin, B. Mutnury","doi":"10.1109/EDAPS.2016.7874408","DOIUrl":"https://doi.org/10.1109/EDAPS.2016.7874408","url":null,"abstract":"The paper discusses challenges of high-speed serial links using multi-level signaling and gives comparison of the performance of the various channels with different lossy materials and equalization options. Advantages and problems of multi-level signaling are shown based on the test results.","PeriodicalId":191549,"journal":{"name":"2016 IEEE Electrical Design of Advanced Packaging and Systems (EDAPS)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123493552","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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