Impact of Backside Defects on Device Characteristics of Ultra-Thin DRAMs with 3-5 μm Si Wafers for Bumpless Build Cube (BBCube) Application

Abstract

To clarify the impact of backside defects on the device characteristics during wafer ultra-thinning, 20 nm-node DRAM Si wafers were thinned down to a thickness of 3-5 μm and evaluated. The dependences of the DRAM characteristics on the depth of backside defects, Si thickness, and chip position within a 300-mm wafer are described.