2GS/s, 10ps Resolution CMOS Differential Time-to-Digital Converter for Real-Time Testing of Source-Synchronous Memory Device

Abstract

A differential time-to-digital converter (TDC), fabricated in 0.18 mum CMOS process, for source-synchronous device testing is demonstrated. It exhibits a maximum sampling rate of 2.133 GS/s, a variable resolution of 10-40 ps, an infinite measurement range, an INL of 8.5 ps(pk-pk), and a jitter of 18.3 ps(pk-pk). It is available to be applied to the jitter histogram measurement without dead-time because it detects all transition timing continuously. Furthermore, a possible application of this TDC to ADC or DAC is suggested.