T. Matsuzaki, T. Onuki, S. Nagatsuka, H. Inoue, T. Ishizu, Y. Ieda, Naoto Yamade, H. Miyairi, M. Sakakura, Y. Shionoiri, K. Kato, T. Okuda, J. Koyama, Yoshitaka Yamamoto, S. Yamazaki
{"title":"A 16-Level-Cell Nonvolatile Memory with Crystalline In-Ga-Zn Oxide FET","authors":"T. Matsuzaki, T. Onuki, S. Nagatsuka, H. Inoue, T. Ishizu, Y. Ieda, Naoto Yamade, H. Miyairi, M. Sakakura, Y. Shionoiri, K. Kato, T. Okuda, J. Koyama, Yoshitaka Yamamoto, S. Yamazaki","doi":"10.1109/IMW.2015.7150266","DOIUrl":null,"url":null,"abstract":"A 16-level cell is demonstrated using a test chip of nonvolatile oxide semiconductor RAM comprising c-axis aligned crystalline In-Ga-Zn oxide FETs. A read circuit composed of voltage followers outputs a read voltage with a maximum distribution of 37 mV. A single voltage follower has a maximum distribution of the read voltage of 25.3 mV. A 200 ns write time of the test chip is demonstrated.","PeriodicalId":107437,"journal":{"name":"2015 IEEE International Memory Workshop (IMW)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2015-05-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2015 IEEE International Memory Workshop (IMW)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IMW.2015.7150266","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
Abstract
A 16-level cell is demonstrated using a test chip of nonvolatile oxide semiconductor RAM comprising c-axis aligned crystalline In-Ga-Zn oxide FETs. A read circuit composed of voltage followers outputs a read voltage with a maximum distribution of 37 mV. A single voltage follower has a maximum distribution of the read voltage of 25.3 mV. A 200 ns write time of the test chip is demonstrated.