Transformation of timing diagram specifications into VHDL code

Abstract

Timing diagrams with data and timing annotations are introduced as a language for specifying interface circuits. In this paper we describe how to generate VHDL from timing diagrams in order to get a hardware implementation or simply to get VHDL code for stimuli to be used in a test bench. By giving timing diagrams a formal semantics in terms of T-LOTOS, we can apply optimizing correctness-preserving transformation steps. In order to produce good VHDL code on the way to a hardware implementation it is of great importance to introduce structures into the final description that are not automatically derivable from a given specification. The designer is rather asked to assist in introducing a structure by applying a bottom-up interactive synthesis procedure.