{"title":"Reliability, testability and yield of majority voting VLSI","authors":"C. Stroud, A. Barbour","doi":"10.1109/ASIC.1990.186155","DOIUrl":null,"url":null,"abstract":"Mathematical models for determining the reliability and yield of VLSI designs incorporating majority voting techniques are developed. Significant reliability and yield improvements are predicted and compared to actual VLSI implementations. By satisfying testability conditions, a unified approach to fault and defect tolerance is achieved.<<ETX>>","PeriodicalId":126693,"journal":{"name":"Third Annual IEEE Proceedings on ASIC Seminar and Exhibit","volume":"21 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1990-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Third Annual IEEE Proceedings on ASIC Seminar and Exhibit","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASIC.1990.186155","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 5
Abstract
Mathematical models for determining the reliability and yield of VLSI designs incorporating majority voting techniques are developed. Significant reliability and yield improvements are predicted and compared to actual VLSI implementations. By satisfying testability conditions, a unified approach to fault and defect tolerance is achieved.<>
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